1 /* 2 * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_H 8 #define ARCH_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * MIDR bit definitions 14 ******************************************************************************/ 15 #define MIDR_IMPL_MASK U(0xff) 16 #define MIDR_IMPL_SHIFT U(24) 17 #define MIDR_VAR_SHIFT U(20) 18 #define MIDR_VAR_BITS U(4) 19 #define MIDR_REV_SHIFT U(0) 20 #define MIDR_REV_BITS U(4) 21 #define MIDR_PN_MASK U(0xfff) 22 #define MIDR_PN_SHIFT U(4) 23 24 /******************************************************************************* 25 * MPIDR macros 26 ******************************************************************************/ 27 #define MPIDR_MT_MASK (U(1) << 24) 28 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 29 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 30 #define MPIDR_AFFINITY_BITS U(8) 31 #define MPIDR_AFFLVL_MASK U(0xff) 32 #define MPIDR_AFFLVL_SHIFT U(3) 33 #define MPIDR_AFF0_SHIFT U(0) 34 #define MPIDR_AFF1_SHIFT U(8) 35 #define MPIDR_AFF2_SHIFT U(16) 36 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 37 #define MPIDR_AFFINITY_MASK U(0x00ffffff) 38 #define MPIDR_AFFLVL0 U(0) 39 #define MPIDR_AFFLVL1 U(1) 40 #define MPIDR_AFFLVL2 U(2) 41 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 42 43 #define MPIDR_AFFLVL0_VAL(mpidr) \ 44 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 45 #define MPIDR_AFFLVL1_VAL(mpidr) \ 46 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 47 #define MPIDR_AFFLVL2_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL3_VAL(mpidr) U(0) 50 51 #define MPIDR_AFF_ID(mpid, n) \ 52 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 53 54 #define MPID_MASK (MPIDR_MT_MASK |\ 55 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)|\ 56 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)|\ 57 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 58 59 /* 60 * An invalid MPID. This value can be used by functions that return an MPID to 61 * indicate an error. 62 */ 63 #define INVALID_MPID U(0xFFFFFFFF) 64 65 /* 66 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 67 * add one while using this macro to define array sizes. 68 */ 69 #define MPIDR_MAX_AFFLVL U(2) 70 71 /* Data Cache set/way op type defines */ 72 #define DC_OP_ISW U(0x0) 73 #define DC_OP_CISW U(0x1) 74 #if ERRATA_A53_827319 75 #define DC_OP_CSW DC_OP_CISW 76 #else 77 #define DC_OP_CSW U(0x2) 78 #endif 79 80 /******************************************************************************* 81 * Generic timer memory mapped registers & offsets 82 ******************************************************************************/ 83 #define CNTCR_OFF U(0x000) 84 /* Counter Count Value Lower register */ 85 #define CNTCVL_OFF U(0x008) 86 /* Counter Count Value Upper register */ 87 #define CNTCVU_OFF U(0x00C) 88 #define CNTFID_OFF U(0x020) 89 90 #define CNTCR_EN (U(1) << 0) 91 #define CNTCR_HDBG (U(1) << 1) 92 #define CNTCR_FCREQ(x) ((x) << 8) 93 94 /******************************************************************************* 95 * System register bit definitions 96 ******************************************************************************/ 97 /* CLIDR definitions */ 98 #define LOUIS_SHIFT U(21) 99 #define LOC_SHIFT U(24) 100 #define CLIDR_FIELD_WIDTH U(3) 101 102 /* CSSELR definitions */ 103 #define LEVEL_SHIFT U(1) 104 105 /* ID_DFR0_EL1 definitions */ 106 #define ID_DFR0_COPTRC_SHIFT U(12) 107 #define ID_DFR0_COPTRC_MASK U(0xf) 108 #define ID_DFR0_COPTRC_SUPPORTED U(1) 109 #define ID_DFR0_COPTRC_LENGTH U(4) 110 111 /* ID_DFR1_EL1 definitions */ 112 #define ID_DFR1_MTPMU_SHIFT U(0) 113 #define ID_DFR1_MTPMU_MASK U(0xf) 114 #define ID_DFR1_MTPMU_SUPPORTED U(1) 115 116 /* ID_MMFR4 definitions */ 117 #define ID_MMFR4_CNP_SHIFT U(12) 118 #define ID_MMFR4_CNP_LENGTH U(4) 119 #define ID_MMFR4_CNP_MASK U(0xf) 120 121 /* ID_PFR0 definitions */ 122 #define ID_PFR0_AMU_SHIFT U(20) 123 #define ID_PFR0_AMU_LENGTH U(4) 124 #define ID_PFR0_AMU_MASK U(0xf) 125 #define ID_PFR0_AMU_NOT_SUPPORTED U(0x0) 126 #define ID_PFR0_AMU_V1 U(0x1) 127 #define ID_PFR0_AMU_V1P1 U(0x2) 128 129 #define ID_PFR0_DIT_SHIFT U(24) 130 #define ID_PFR0_DIT_LENGTH U(4) 131 #define ID_PFR0_DIT_MASK U(0xf) 132 #define ID_PFR0_DIT_SUPPORTED (U(1) << ID_PFR0_DIT_SHIFT) 133 134 /* ID_PFR1 definitions */ 135 #define ID_PFR1_VIRTEXT_SHIFT U(12) 136 #define ID_PFR1_VIRTEXT_MASK U(0xf) 137 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 138 & ID_PFR1_VIRTEXT_MASK) 139 #define ID_PFR1_GENTIMER_SHIFT U(16) 140 #define ID_PFR1_GENTIMER_MASK U(0xf) 141 #define ID_PFR1_GIC_SHIFT U(28) 142 #define ID_PFR1_GIC_MASK U(0xf) 143 #define ID_PFR1_SEC_SHIFT U(4) 144 #define ID_PFR1_SEC_MASK U(0xf) 145 #define ID_PFR1_ELx_ENABLED U(1) 146 147 /* SCTLR definitions */ 148 #define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \ 149 (U(1) << 3)) 150 #if ARM_ARCH_MAJOR == 7 151 #define SCTLR_RES1 SCTLR_RES1_DEF 152 #else 153 #define SCTLR_RES1 (SCTLR_RES1_DEF | (U(1) << 11)) 154 #endif 155 #define SCTLR_M_BIT (U(1) << 0) 156 #define SCTLR_A_BIT (U(1) << 1) 157 #define SCTLR_C_BIT (U(1) << 2) 158 #define SCTLR_CP15BEN_BIT (U(1) << 5) 159 #define SCTLR_ITD_BIT (U(1) << 7) 160 #define SCTLR_Z_BIT (U(1) << 11) 161 #define SCTLR_I_BIT (U(1) << 12) 162 #define SCTLR_V_BIT (U(1) << 13) 163 #define SCTLR_RR_BIT (U(1) << 14) 164 #define SCTLR_NTWI_BIT (U(1) << 16) 165 #define SCTLR_NTWE_BIT (U(1) << 18) 166 #define SCTLR_WXN_BIT (U(1) << 19) 167 #define SCTLR_UWXN_BIT (U(1) << 20) 168 #define SCTLR_EE_BIT (U(1) << 25) 169 #define SCTLR_TRE_BIT (U(1) << 28) 170 #define SCTLR_AFE_BIT (U(1) << 29) 171 #define SCTLR_TE_BIT (U(1) << 30) 172 #define SCTLR_DSSBS_BIT (U(1) << 31) 173 #define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \ 174 SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT) 175 176 /* SDCR definitions */ 177 #define SDCR_SPD(x) ((x) << 14) 178 #define SDCR_SPD_LEGACY U(0x0) 179 #define SDCR_SPD_DISABLE U(0x2) 180 #define SDCR_SPD_ENABLE U(0x3) 181 #define SDCR_SCCD_BIT (U(1) << 23) 182 #define SDCR_SPME_BIT (U(1) << 17) 183 #define SDCR_RESET_VAL U(0x0) 184 #define SDCR_MTPME_BIT (U(1) << 28) 185 186 /* HSCTLR definitions */ 187 #define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 188 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 189 (U(1) << 11) | (U(1) << 4) | (U(1) << 3)) 190 191 #define HSCTLR_M_BIT (U(1) << 0) 192 #define HSCTLR_A_BIT (U(1) << 1) 193 #define HSCTLR_C_BIT (U(1) << 2) 194 #define HSCTLR_CP15BEN_BIT (U(1) << 5) 195 #define HSCTLR_ITD_BIT (U(1) << 7) 196 #define HSCTLR_SED_BIT (U(1) << 8) 197 #define HSCTLR_I_BIT (U(1) << 12) 198 #define HSCTLR_WXN_BIT (U(1) << 19) 199 #define HSCTLR_EE_BIT (U(1) << 25) 200 #define HSCTLR_TE_BIT (U(1) << 30) 201 202 /* CPACR definitions */ 203 #define CPACR_FPEN(x) ((x) << 20) 204 #define CPACR_FP_TRAP_PL0 UL(0x1) 205 #define CPACR_FP_TRAP_ALL UL(0x2) 206 #define CPACR_FP_TRAP_NONE UL(0x3) 207 208 /* SCR definitions */ 209 #define SCR_TWE_BIT (UL(1) << 13) 210 #define SCR_TWI_BIT (UL(1) << 12) 211 #define SCR_SIF_BIT (UL(1) << 9) 212 #define SCR_HCE_BIT (UL(1) << 8) 213 #define SCR_SCD_BIT (UL(1) << 7) 214 #define SCR_NET_BIT (UL(1) << 6) 215 #define SCR_AW_BIT (UL(1) << 5) 216 #define SCR_FW_BIT (UL(1) << 4) 217 #define SCR_EA_BIT (UL(1) << 3) 218 #define SCR_FIQ_BIT (UL(1) << 2) 219 #define SCR_IRQ_BIT (UL(1) << 1) 220 #define SCR_NS_BIT (UL(1) << 0) 221 #define SCR_VALID_BIT_MASK U(0x33ff) 222 #define SCR_RESET_VAL U(0x0) 223 224 #define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT) 225 226 /* HCR definitions */ 227 #define HCR_TGE_BIT (U(1) << 27) 228 #define HCR_AMO_BIT (U(1) << 5) 229 #define HCR_IMO_BIT (U(1) << 4) 230 #define HCR_FMO_BIT (U(1) << 3) 231 #define HCR_RESET_VAL U(0x0) 232 233 /* CNTHCTL definitions */ 234 #define CNTHCTL_RESET_VAL U(0x0) 235 #define PL1PCEN_BIT (U(1) << 1) 236 #define PL1PCTEN_BIT (U(1) << 0) 237 238 /* CNTKCTL definitions */ 239 #define PL0PTEN_BIT (U(1) << 9) 240 #define PL0VTEN_BIT (U(1) << 8) 241 #define PL0PCTEN_BIT (U(1) << 0) 242 #define PL0VCTEN_BIT (U(1) << 1) 243 #define EVNTEN_BIT (U(1) << 2) 244 #define EVNTDIR_BIT (U(1) << 3) 245 #define EVNTI_SHIFT U(4) 246 #define EVNTI_MASK U(0xf) 247 248 /* HCPTR definitions */ 249 #define HCPTR_RES1 ((U(1) << 13) | (U(1) << 12) | U(0x3ff)) 250 #define TCPAC_BIT (U(1) << 31) 251 #define TAM_BIT (U(1) << 30) 252 #define TTA_BIT (U(1) << 20) 253 #define TCP11_BIT (U(1) << 11) 254 #define TCP10_BIT (U(1) << 10) 255 #define HCPTR_RESET_VAL HCPTR_RES1 256 257 /* VTTBR defintions */ 258 #define VTTBR_RESET_VAL ULL(0x0) 259 #define VTTBR_VMID_MASK ULL(0xff) 260 #define VTTBR_VMID_SHIFT U(48) 261 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 262 #define VTTBR_BADDR_SHIFT U(0) 263 264 /* HDCR definitions */ 265 #define HDCR_MTPME_BIT (U(1) << 28) 266 #define HDCR_HLP_BIT (U(1) << 26) 267 #define HDCR_HPME_BIT (U(1) << 7) 268 #define HDCR_RESET_VAL U(0x0) 269 270 /* HSTR definitions */ 271 #define HSTR_RESET_VAL U(0x0) 272 273 /* CNTHP_CTL definitions */ 274 #define CNTHP_CTL_RESET_VAL U(0x0) 275 276 /* NSACR definitions */ 277 #define NSASEDIS_BIT (U(1) << 15) 278 #define NSTRCDIS_BIT (U(1) << 20) 279 #define NSACR_CP11_BIT (U(1) << 11) 280 #define NSACR_CP10_BIT (U(1) << 10) 281 #define NSACR_IMP_DEF_MASK (U(0x7) << 16) 282 #define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT) 283 #define NSACR_RESET_VAL U(0x0) 284 285 /* CPACR definitions */ 286 #define ASEDIS_BIT (U(1) << 31) 287 #define TRCDIS_BIT (U(1) << 28) 288 #define CPACR_CP11_SHIFT U(22) 289 #define CPACR_CP10_SHIFT U(20) 290 #define CPACR_ENABLE_FP_ACCESS ((U(0x3) << CPACR_CP11_SHIFT) |\ 291 (U(0x3) << CPACR_CP10_SHIFT)) 292 #define CPACR_RESET_VAL U(0x0) 293 294 /* FPEXC definitions */ 295 #define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8)) 296 #define FPEXC_EN_BIT (U(1) << 30) 297 #define FPEXC_RESET_VAL FPEXC_RES1 298 299 /* SPSR/CPSR definitions */ 300 #define SPSR_FIQ_BIT (U(1) << 0) 301 #define SPSR_IRQ_BIT (U(1) << 1) 302 #define SPSR_ABT_BIT (U(1) << 2) 303 #define SPSR_AIF_SHIFT U(6) 304 #define SPSR_AIF_MASK U(0x7) 305 306 #define SPSR_E_SHIFT U(9) 307 #define SPSR_E_MASK U(0x1) 308 #define SPSR_E_LITTLE U(0) 309 #define SPSR_E_BIG U(1) 310 311 #define SPSR_T_SHIFT U(5) 312 #define SPSR_T_MASK U(0x1) 313 #define SPSR_T_ARM U(0) 314 #define SPSR_T_THUMB U(1) 315 316 #define SPSR_MODE_SHIFT U(0) 317 #define SPSR_MODE_MASK U(0x7) 318 319 #define SPSR_SSBS_BIT BIT_32(23) 320 321 #define DISABLE_ALL_EXCEPTIONS \ 322 (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT) 323 324 #define CPSR_DIT_BIT (U(1) << 21) 325 /* 326 * TTBCR definitions 327 */ 328 #define TTBCR_EAE_BIT (U(1) << 31) 329 330 #define TTBCR_SH1_NON_SHAREABLE (U(0x0) << 28) 331 #define TTBCR_SH1_OUTER_SHAREABLE (U(0x2) << 28) 332 #define TTBCR_SH1_INNER_SHAREABLE (U(0x3) << 28) 333 334 #define TTBCR_RGN1_OUTER_NC (U(0x0) << 26) 335 #define TTBCR_RGN1_OUTER_WBA (U(0x1) << 26) 336 #define TTBCR_RGN1_OUTER_WT (U(0x2) << 26) 337 #define TTBCR_RGN1_OUTER_WBNA (U(0x3) << 26) 338 339 #define TTBCR_RGN1_INNER_NC (U(0x0) << 24) 340 #define TTBCR_RGN1_INNER_WBA (U(0x1) << 24) 341 #define TTBCR_RGN1_INNER_WT (U(0x2) << 24) 342 #define TTBCR_RGN1_INNER_WBNA (U(0x3) << 24) 343 344 #define TTBCR_EPD1_BIT (U(1) << 23) 345 #define TTBCR_A1_BIT (U(1) << 22) 346 347 #define TTBCR_T1SZ_SHIFT U(16) 348 #define TTBCR_T1SZ_MASK U(0x7) 349 #define TTBCR_TxSZ_MIN U(0) 350 #define TTBCR_TxSZ_MAX U(7) 351 352 #define TTBCR_SH0_NON_SHAREABLE (U(0x0) << 12) 353 #define TTBCR_SH0_OUTER_SHAREABLE (U(0x2) << 12) 354 #define TTBCR_SH0_INNER_SHAREABLE (U(0x3) << 12) 355 356 #define TTBCR_RGN0_OUTER_NC (U(0x0) << 10) 357 #define TTBCR_RGN0_OUTER_WBA (U(0x1) << 10) 358 #define TTBCR_RGN0_OUTER_WT (U(0x2) << 10) 359 #define TTBCR_RGN0_OUTER_WBNA (U(0x3) << 10) 360 361 #define TTBCR_RGN0_INNER_NC (U(0x0) << 8) 362 #define TTBCR_RGN0_INNER_WBA (U(0x1) << 8) 363 #define TTBCR_RGN0_INNER_WT (U(0x2) << 8) 364 #define TTBCR_RGN0_INNER_WBNA (U(0x3) << 8) 365 366 #define TTBCR_EPD0_BIT (U(1) << 7) 367 #define TTBCR_T0SZ_SHIFT U(0) 368 #define TTBCR_T0SZ_MASK U(0x7) 369 370 /* 371 * HTCR definitions 372 */ 373 #define HTCR_RES1 ((U(1) << 31) | (U(1) << 23)) 374 375 #define HTCR_SH0_NON_SHAREABLE (U(0x0) << 12) 376 #define HTCR_SH0_OUTER_SHAREABLE (U(0x2) << 12) 377 #define HTCR_SH0_INNER_SHAREABLE (U(0x3) << 12) 378 379 #define HTCR_RGN0_OUTER_NC (U(0x0) << 10) 380 #define HTCR_RGN0_OUTER_WBA (U(0x1) << 10) 381 #define HTCR_RGN0_OUTER_WT (U(0x2) << 10) 382 #define HTCR_RGN0_OUTER_WBNA (U(0x3) << 10) 383 384 #define HTCR_RGN0_INNER_NC (U(0x0) << 8) 385 #define HTCR_RGN0_INNER_WBA (U(0x1) << 8) 386 #define HTCR_RGN0_INNER_WT (U(0x2) << 8) 387 #define HTCR_RGN0_INNER_WBNA (U(0x3) << 8) 388 389 #define HTCR_T0SZ_SHIFT U(0) 390 #define HTCR_T0SZ_MASK U(0x7) 391 392 #define MODE_RW_SHIFT U(0x4) 393 #define MODE_RW_MASK U(0x1) 394 #define MODE_RW_32 U(0x1) 395 396 #define MODE32_SHIFT U(0) 397 #define MODE32_MASK U(0x1f) 398 #define MODE32_usr U(0x10) 399 #define MODE32_fiq U(0x11) 400 #define MODE32_irq U(0x12) 401 #define MODE32_svc U(0x13) 402 #define MODE32_mon U(0x16) 403 #define MODE32_abt U(0x17) 404 #define MODE32_hyp U(0x1a) 405 #define MODE32_und U(0x1b) 406 #define MODE32_sys U(0x1f) 407 408 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 409 410 #define SPSR_MODE32(mode, isa, endian, aif) \ 411 ( \ 412 ( \ 413 (MODE_RW_32 << MODE_RW_SHIFT) | \ 414 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 415 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 416 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 417 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) \ 418 ) & \ 419 (~(SPSR_SSBS_BIT)) \ 420 ) 421 422 /* 423 * TTBR definitions 424 */ 425 #define TTBR_CNP_BIT ULL(0x1) 426 427 /* 428 * CTR definitions 429 */ 430 #define CTR_CWG_SHIFT U(24) 431 #define CTR_CWG_MASK U(0xf) 432 #define CTR_ERG_SHIFT U(20) 433 #define CTR_ERG_MASK U(0xf) 434 #define CTR_DMINLINE_SHIFT U(16) 435 #define CTR_DMINLINE_WIDTH U(4) 436 #define CTR_DMINLINE_MASK ((U(1) << 4) - U(1)) 437 #define CTR_L1IP_SHIFT U(14) 438 #define CTR_L1IP_MASK U(0x3) 439 #define CTR_IMINLINE_SHIFT U(0) 440 #define CTR_IMINLINE_MASK U(0xf) 441 442 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 443 444 /* PMCR definitions */ 445 #define PMCR_N_SHIFT U(11) 446 #define PMCR_N_MASK U(0x1f) 447 #define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT) 448 #define PMCR_LP_BIT (U(1) << 7) 449 #define PMCR_LC_BIT (U(1) << 6) 450 #define PMCR_DP_BIT (U(1) << 5) 451 #define PMCR_RESET_VAL U(0x0) 452 453 /******************************************************************************* 454 * Definitions of register offsets, fields and macros for CPU system 455 * instructions. 456 ******************************************************************************/ 457 458 #define TLBI_ADDR_SHIFT U(0) 459 #define TLBI_ADDR_MASK U(0xFFFFF000) 460 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 461 462 /******************************************************************************* 463 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 464 * system level implementation of the Generic Timer. 465 ******************************************************************************/ 466 #define CNTCTLBASE_CNTFRQ U(0x0) 467 #define CNTNSAR U(0x4) 468 #define CNTNSAR_NS_SHIFT(x) (x) 469 470 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 471 #define CNTACR_RPCT_SHIFT U(0x0) 472 #define CNTACR_RVCT_SHIFT U(0x1) 473 #define CNTACR_RFRQ_SHIFT U(0x2) 474 #define CNTACR_RVOFF_SHIFT U(0x3) 475 #define CNTACR_RWVT_SHIFT U(0x4) 476 #define CNTACR_RWPT_SHIFT U(0x5) 477 478 /******************************************************************************* 479 * Definitions of register offsets and fields in the CNTBaseN Frame of the 480 * system level implementation of the Generic Timer. 481 ******************************************************************************/ 482 /* Physical Count register. */ 483 #define CNTPCT_LO U(0x0) 484 /* Counter Frequency register. */ 485 #define CNTBASEN_CNTFRQ U(0x10) 486 /* Physical Timer CompareValue register. */ 487 #define CNTP_CVAL_LO U(0x20) 488 /* Physical Timer Control register. */ 489 #define CNTP_CTL U(0x2c) 490 491 /* Physical timer control register bit fields shifts and masks */ 492 #define CNTP_CTL_ENABLE_SHIFT 0 493 #define CNTP_CTL_IMASK_SHIFT 1 494 #define CNTP_CTL_ISTATUS_SHIFT 2 495 496 #define CNTP_CTL_ENABLE_MASK U(1) 497 #define CNTP_CTL_IMASK_MASK U(1) 498 #define CNTP_CTL_ISTATUS_MASK U(1) 499 500 /* MAIR macros */ 501 #define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << U(3))) 502 #define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << U(3))) 503 504 /* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */ 505 #define SCR p15, 0, c1, c1, 0 506 #define SCTLR p15, 0, c1, c0, 0 507 #define ACTLR p15, 0, c1, c0, 1 508 #define SDCR p15, 0, c1, c3, 1 509 #define MPIDR p15, 0, c0, c0, 5 510 #define MIDR p15, 0, c0, c0, 0 511 #define HVBAR p15, 4, c12, c0, 0 512 #define VBAR p15, 0, c12, c0, 0 513 #define MVBAR p15, 0, c12, c0, 1 514 #define NSACR p15, 0, c1, c1, 2 515 #define CPACR p15, 0, c1, c0, 2 516 #define DCCIMVAC p15, 0, c7, c14, 1 517 #define DCCMVAC p15, 0, c7, c10, 1 518 #define DCIMVAC p15, 0, c7, c6, 1 519 #define DCCISW p15, 0, c7, c14, 2 520 #define DCCSW p15, 0, c7, c10, 2 521 #define DCISW p15, 0, c7, c6, 2 522 #define CTR p15, 0, c0, c0, 1 523 #define CNTFRQ p15, 0, c14, c0, 0 524 #define ID_MMFR4 p15, 0, c0, c2, 6 525 #define ID_DFR0 p15, 0, c0, c1, 2 526 #define ID_DFR1 p15, 0, c0, c3, 5 527 #define ID_PFR0 p15, 0, c0, c1, 0 528 #define ID_PFR1 p15, 0, c0, c1, 1 529 #define MAIR0 p15, 0, c10, c2, 0 530 #define MAIR1 p15, 0, c10, c2, 1 531 #define TTBCR p15, 0, c2, c0, 2 532 #define TTBR0 p15, 0, c2, c0, 0 533 #define TTBR1 p15, 0, c2, c0, 1 534 #define TLBIALL p15, 0, c8, c7, 0 535 #define TLBIALLH p15, 4, c8, c7, 0 536 #define TLBIALLIS p15, 0, c8, c3, 0 537 #define TLBIMVA p15, 0, c8, c7, 1 538 #define TLBIMVAA p15, 0, c8, c7, 3 539 #define TLBIMVAAIS p15, 0, c8, c3, 3 540 #define TLBIMVAHIS p15, 4, c8, c3, 1 541 #define BPIALLIS p15, 0, c7, c1, 6 542 #define BPIALL p15, 0, c7, c5, 6 543 #define ICIALLU p15, 0, c7, c5, 0 544 #define HSCTLR p15, 4, c1, c0, 0 545 #define HCR p15, 4, c1, c1, 0 546 #define HCPTR p15, 4, c1, c1, 2 547 #define HSTR p15, 4, c1, c1, 3 548 #define CNTHCTL p15, 4, c14, c1, 0 549 #define CNTKCTL p15, 0, c14, c1, 0 550 #define VPIDR p15, 4, c0, c0, 0 551 #define VMPIDR p15, 4, c0, c0, 5 552 #define ISR p15, 0, c12, c1, 0 553 #define CLIDR p15, 1, c0, c0, 1 554 #define CSSELR p15, 2, c0, c0, 0 555 #define CCSIDR p15, 1, c0, c0, 0 556 #define HTCR p15, 4, c2, c0, 2 557 #define HMAIR0 p15, 4, c10, c2, 0 558 #define ATS1CPR p15, 0, c7, c8, 0 559 #define ATS1HR p15, 4, c7, c8, 0 560 #define DBGOSDLR p14, 0, c1, c3, 4 561 562 /* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ 563 #define HDCR p15, 4, c1, c1, 1 564 #define PMCR p15, 0, c9, c12, 0 565 #define CNTHP_TVAL p15, 4, c14, c2, 0 566 #define CNTHP_CTL p15, 4, c14, c2, 1 567 568 /* AArch32 coproc registers for 32bit MMU descriptor support */ 569 #define PRRR p15, 0, c10, c2, 0 570 #define NMRR p15, 0, c10, c2, 1 571 #define DACR p15, 0, c3, c0, 0 572 573 /* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ 574 #define ICC_IAR1 p15, 0, c12, c12, 0 575 #define ICC_IAR0 p15, 0, c12, c8, 0 576 #define ICC_EOIR1 p15, 0, c12, c12, 1 577 #define ICC_EOIR0 p15, 0, c12, c8, 1 578 #define ICC_HPPIR1 p15, 0, c12, c12, 2 579 #define ICC_HPPIR0 p15, 0, c12, c8, 2 580 #define ICC_BPR1 p15, 0, c12, c12, 3 581 #define ICC_BPR0 p15, 0, c12, c8, 3 582 #define ICC_DIR p15, 0, c12, c11, 1 583 #define ICC_PMR p15, 0, c4, c6, 0 584 #define ICC_RPR p15, 0, c12, c11, 3 585 #define ICC_CTLR p15, 0, c12, c12, 4 586 #define ICC_MCTLR p15, 6, c12, c12, 4 587 #define ICC_SRE p15, 0, c12, c12, 5 588 #define ICC_HSRE p15, 4, c12, c9, 5 589 #define ICC_MSRE p15, 6, c12, c12, 5 590 #define ICC_IGRPEN0 p15, 0, c12, c12, 6 591 #define ICC_IGRPEN1 p15, 0, c12, c12, 7 592 #define ICC_MGRPEN1 p15, 6, c12, c12, 7 593 594 /* 64 bit system register defines The format is: coproc, opt1, CRm */ 595 #define TTBR0_64 p15, 0, c2 596 #define TTBR1_64 p15, 1, c2 597 #define CNTVOFF_64 p15, 4, c14 598 #define VTTBR_64 p15, 6, c2 599 #define CNTPCT_64 p15, 0, c14 600 #define HTTBR_64 p15, 4, c2 601 #define CNTHP_CVAL_64 p15, 6, c14 602 #define PAR_64 p15, 0, c7 603 604 /* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */ 605 #define ICC_SGI1R_EL1_64 p15, 0, c12 606 #define ICC_ASGI1R_EL1_64 p15, 1, c12 607 #define ICC_SGI0R_EL1_64 p15, 2, c12 608 609 /******************************************************************************* 610 * Definitions of MAIR encodings for device and normal memory 611 ******************************************************************************/ 612 /* 613 * MAIR encodings for device memory attributes. 614 */ 615 #define MAIR_DEV_nGnRnE U(0x0) 616 #define MAIR_DEV_nGnRE U(0x4) 617 #define MAIR_DEV_nGRE U(0x8) 618 #define MAIR_DEV_GRE U(0xc) 619 620 /* 621 * MAIR encodings for normal memory attributes. 622 * 623 * Cache Policy 624 * WT: Write Through 625 * WB: Write Back 626 * NC: Non-Cacheable 627 * 628 * Transient Hint 629 * NTR: Non-Transient 630 * TR: Transient 631 * 632 * Allocation Policy 633 * RA: Read Allocate 634 * WA: Write Allocate 635 * RWA: Read and Write Allocate 636 * NA: No Allocation 637 */ 638 #define MAIR_NORM_WT_TR_WA U(0x1) 639 #define MAIR_NORM_WT_TR_RA U(0x2) 640 #define MAIR_NORM_WT_TR_RWA U(0x3) 641 #define MAIR_NORM_NC U(0x4) 642 #define MAIR_NORM_WB_TR_WA U(0x5) 643 #define MAIR_NORM_WB_TR_RA U(0x6) 644 #define MAIR_NORM_WB_TR_RWA U(0x7) 645 #define MAIR_NORM_WT_NTR_NA U(0x8) 646 #define MAIR_NORM_WT_NTR_WA U(0x9) 647 #define MAIR_NORM_WT_NTR_RA U(0xa) 648 #define MAIR_NORM_WT_NTR_RWA U(0xb) 649 #define MAIR_NORM_WB_NTR_NA U(0xc) 650 #define MAIR_NORM_WB_NTR_WA U(0xd) 651 #define MAIR_NORM_WB_NTR_RA U(0xe) 652 #define MAIR_NORM_WB_NTR_RWA U(0xf) 653 654 #define MAIR_NORM_OUTER_SHIFT U(4) 655 656 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 657 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 658 659 /* PAR fields */ 660 #define PAR_F_SHIFT U(0) 661 #define PAR_F_MASK ULL(0x1) 662 #define PAR_ADDR_SHIFT U(12) 663 #define PAR_ADDR_MASK (BIT_64(40) - ULL(1)) /* 40-bits-wide page address */ 664 665 /******************************************************************************* 666 * Definitions for system register interface to AMU for FEAT_AMUv1 667 ******************************************************************************/ 668 #define AMCR p15, 0, c13, c2, 0 669 #define AMCFGR p15, 0, c13, c2, 1 670 #define AMCGCR p15, 0, c13, c2, 2 671 #define AMUSERENR p15, 0, c13, c2, 3 672 #define AMCNTENCLR0 p15, 0, c13, c2, 4 673 #define AMCNTENSET0 p15, 0, c13, c2, 5 674 #define AMCNTENCLR1 p15, 0, c13, c3, 0 675 #define AMCNTENSET1 p15, 0, c13, c3, 1 676 677 /* Activity Monitor Group 0 Event Counter Registers */ 678 #define AMEVCNTR00 p15, 0, c0 679 #define AMEVCNTR01 p15, 1, c0 680 #define AMEVCNTR02 p15, 2, c0 681 #define AMEVCNTR03 p15, 3, c0 682 683 /* Activity Monitor Group 0 Event Type Registers */ 684 #define AMEVTYPER00 p15, 0, c13, c6, 0 685 #define AMEVTYPER01 p15, 0, c13, c6, 1 686 #define AMEVTYPER02 p15, 0, c13, c6, 2 687 #define AMEVTYPER03 p15, 0, c13, c6, 3 688 689 /* Activity Monitor Group 1 Event Counter Registers */ 690 #define AMEVCNTR10 p15, 0, c4 691 #define AMEVCNTR11 p15, 1, c4 692 #define AMEVCNTR12 p15, 2, c4 693 #define AMEVCNTR13 p15, 3, c4 694 #define AMEVCNTR14 p15, 4, c4 695 #define AMEVCNTR15 p15, 5, c4 696 #define AMEVCNTR16 p15, 6, c4 697 #define AMEVCNTR17 p15, 7, c4 698 #define AMEVCNTR18 p15, 0, c5 699 #define AMEVCNTR19 p15, 1, c5 700 #define AMEVCNTR1A p15, 2, c5 701 #define AMEVCNTR1B p15, 3, c5 702 #define AMEVCNTR1C p15, 4, c5 703 #define AMEVCNTR1D p15, 5, c5 704 #define AMEVCNTR1E p15, 6, c5 705 #define AMEVCNTR1F p15, 7, c5 706 707 /* Activity Monitor Group 1 Event Type Registers */ 708 #define AMEVTYPER10 p15, 0, c13, c14, 0 709 #define AMEVTYPER11 p15, 0, c13, c14, 1 710 #define AMEVTYPER12 p15, 0, c13, c14, 2 711 #define AMEVTYPER13 p15, 0, c13, c14, 3 712 #define AMEVTYPER14 p15, 0, c13, c14, 4 713 #define AMEVTYPER15 p15, 0, c13, c14, 5 714 #define AMEVTYPER16 p15, 0, c13, c14, 6 715 #define AMEVTYPER17 p15, 0, c13, c14, 7 716 #define AMEVTYPER18 p15, 0, c13, c15, 0 717 #define AMEVTYPER19 p15, 0, c13, c15, 1 718 #define AMEVTYPER1A p15, 0, c13, c15, 2 719 #define AMEVTYPER1B p15, 0, c13, c15, 3 720 #define AMEVTYPER1C p15, 0, c13, c15, 4 721 #define AMEVTYPER1D p15, 0, c13, c15, 5 722 #define AMEVTYPER1E p15, 0, c13, c15, 6 723 #define AMEVTYPER1F p15, 0, c13, c15, 7 724 725 /* AMCR definitions */ 726 #define AMCR_CG1RZ_BIT (ULL(1) << 17) 727 728 /* AMCFGR definitions */ 729 #define AMCFGR_NCG_SHIFT U(28) 730 #define AMCFGR_NCG_MASK U(0xf) 731 #define AMCFGR_N_SHIFT U(0) 732 #define AMCFGR_N_MASK U(0xff) 733 734 /* AMCGCR definitions */ 735 #define AMCGCR_CG1NC_SHIFT U(8) 736 #define AMCGCR_CG1NC_MASK U(0xff) 737 738 /******************************************************************************* 739 * Definitions for DynamicIQ Shared Unit registers 740 ******************************************************************************/ 741 #define CLUSTERPWRDN p15, 0, c15, c3, 6 742 743 /* CLUSTERPWRDN register definitions */ 744 #define DSU_CLUSTER_PWR_OFF 0 745 #define DSU_CLUSTER_PWR_ON 1 746 #define DSU_CLUSTER_PWR_MASK U(1) 747 748 #endif /* ARCH_H */ 749