1 /* 2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef AMU_H 8 #define AMU_H 9 10 #include <stdbool.h> 11 #include <stdint.h> 12 13 #include <lib/cassert.h> 14 #include <lib/utils_def.h> 15 16 #include <context.h> 17 #include <platform_def.h> 18 19 /* All group 0 counters */ 20 #define AMU_GROUP0_COUNTERS_MASK U(0xf) 21 #define AMU_GROUP0_NR_COUNTERS U(4) 22 23 #define AMU_GROUP1_COUNTERS_MASK U(0) 24 25 /* Calculate number of group 1 counters */ 26 #if (AMU_GROUP1_COUNTERS_MASK & (1 << 15)) 27 #define AMU_GROUP1_NR_COUNTERS 16U 28 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 14)) 29 #define AMU_GROUP1_NR_COUNTERS 15U 30 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 13)) 31 #define AMU_GROUP1_NR_COUNTERS 14U 32 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 12)) 33 #define AMU_GROUP1_NR_COUNTERS 13U 34 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 11)) 35 #define AMU_GROUP1_NR_COUNTERS 12U 36 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 10)) 37 #define AMU_GROUP1_NR_COUNTERS 11U 38 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 9)) 39 #define AMU_GROUP1_NR_COUNTERS 10U 40 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 8)) 41 #define AMU_GROUP1_NR_COUNTERS 9U 42 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 7)) 43 #define AMU_GROUP1_NR_COUNTERS 8U 44 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 6)) 45 #define AMU_GROUP1_NR_COUNTERS 7U 46 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 5)) 47 #define AMU_GROUP1_NR_COUNTERS 6U 48 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 4)) 49 #define AMU_GROUP1_NR_COUNTERS 5U 50 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 3)) 51 #define AMU_GROUP1_NR_COUNTERS 4U 52 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 2)) 53 #define AMU_GROUP1_NR_COUNTERS 3U 54 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 1)) 55 #define AMU_GROUP1_NR_COUNTERS 2U 56 #elif (AMU_GROUP1_COUNTERS_MASK & (1 << 0)) 57 #define AMU_GROUP1_NR_COUNTERS 1U 58 #else 59 #define AMU_GROUP1_NR_COUNTERS 0U 60 #endif 61 62 CASSERT(AMU_GROUP1_COUNTERS_MASK <= 0xffff, invalid_amu_group1_counters_mask); 63 64 struct amu_ctx { 65 uint64_t group0_cnts[AMU_GROUP0_NR_COUNTERS]; 66 #if __aarch64__ 67 /* Architected event counter 1 does not have an offset register. */ 68 uint64_t group0_voffsets[AMU_GROUP0_NR_COUNTERS-1]; 69 #endif 70 71 #if AMU_GROUP1_NR_COUNTERS 72 uint64_t group1_cnts[AMU_GROUP1_NR_COUNTERS]; 73 #if __aarch64__ 74 uint64_t group1_voffsets[AMU_GROUP1_NR_COUNTERS]; 75 #endif 76 #endif 77 }; 78 79 unsigned int amu_get_version(void); 80 #if __aarch64__ 81 void amu_enable(bool el2_unused, cpu_context_t *ctx); 82 #else 83 void amu_enable(bool el2_unused); 84 #endif 85 86 /* Group 0 configuration helpers */ 87 uint64_t amu_group0_cnt_read(unsigned int idx); 88 void amu_group0_cnt_write(unsigned int idx, uint64_t val); 89 90 #if __aarch64__ 91 uint64_t amu_group0_voffset_read(unsigned int idx); 92 void amu_group0_voffset_write(unsigned int idx, uint64_t val); 93 #endif 94 95 #if AMU_GROUP1_NR_COUNTERS 96 bool amu_group1_supported(void); 97 98 /* Group 1 configuration helpers */ 99 uint64_t amu_group1_cnt_read(unsigned int idx); 100 void amu_group1_cnt_write(unsigned int idx, uint64_t val); 101 void amu_group1_set_evtype(unsigned int idx, unsigned int val); 102 103 #if __aarch64__ 104 uint64_t amu_group1_voffset_read(unsigned int idx); 105 void amu_group1_voffset_write(unsigned int idx, uint64_t val); 106 #endif 107 108 #endif 109 110 #endif /* AMU_H */ 111