1# 2# Copyright (c) 2016-2021, ARM Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture feature modifiers: none by default 23ARM_ARCH_FEATURE := none 24 25# ARM Architecture major and minor versions: 8.0 by default. 26ARM_ARCH_MAJOR := 8 27ARM_ARCH_MINOR := 0 28 29# Base commit to perform code check on 30BASE_COMMIT := origin/master 31 32# Execute BL2 at EL3 33BL2_AT_EL3 := 0 34 35# Only use SP packages if SP layout JSON is defined 36BL2_ENABLE_SP_LOAD := 0 37 38# BL2 image is stored in XIP memory, for now, this option is only supported 39# when BL2_AT_EL3 is 1. 40BL2_IN_XIP_MEM := 0 41 42# Do dcache invalidate upon BL2 entry at EL3 43BL2_INV_DCACHE := 1 44 45# Select the branch protection features to use. 46BRANCH_PROTECTION := 0 47 48# By default, consider that the platform may release several CPUs out of reset. 49# The platform Makefile is free to override this value. 50COLD_BOOT_SINGLE_CPU := 0 51 52# Flag to compile in coreboot support code. Exclude by default. The coreboot 53# Makefile system will set this when compiling TF as part of a coreboot image. 54COREBOOT := 0 55 56# For Chain of Trust 57CREATE_KEYS := 1 58 59# Build flag to include AArch32 registers in cpu context save and restore during 60# world switch. This flag must be set to 0 for AArch64-only platforms. 61CTX_INCLUDE_AARCH32_REGS := 1 62 63# Include FP registers in cpu context 64CTX_INCLUDE_FPREGS := 0 65 66# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This 67# must be set to 1 if the platform wants to use this feature in the Secure 68# world. It is not needed to use it in the Non-secure world. 69CTX_INCLUDE_PAUTH_REGS := 0 70 71# Include Nested virtualization control (Armv8.4-NV) registers in cpu context. 72# This must be set to 1 if architecture implements Nested Virtualization 73# Extension and platform wants to use this feature in the Secure world 74CTX_INCLUDE_NEVE_REGS := 0 75 76# Debug build 77DEBUG := 0 78 79# By default disable authenticated decryption support. 80DECRYPTION_SUPPORT := none 81 82# Build platform 83DEFAULT_PLAT := fvp 84 85# Disable the generation of the binary image (ELF only). 86DISABLE_BIN_GENERATION := 0 87 88# Disable MTPMU if FEAT_MTPMU is supported. Default is 0 to keep backwards 89# compatibility. 90DISABLE_MTPMU := 0 91 92# Enable capability to disable authentication dynamically. Only meant for 93# development platforms. 94DYN_DISABLE_AUTH := 0 95 96# Build option to enable MPAM for lower ELs 97ENABLE_MPAM_FOR_LOWER_ELS := 0 98 99# Flag to Enable Position Independant support (PIE) 100ENABLE_PIE := 0 101 102# Flag to enable Performance Measurement Framework 103ENABLE_PMF := 0 104 105# Flag to enable PSCI STATs functionality 106ENABLE_PSCI_STAT := 0 107 108# Flag to enable runtime instrumentation using PMF 109ENABLE_RUNTIME_INSTRUMENTATION := 0 110 111# Flag to enable stack corruption protection 112ENABLE_STACK_PROTECTOR := 0 113 114# Flag to enable exception handling in EL3 115EL3_EXCEPTION_HANDLING := 0 116 117# Flag to enable Branch Target Identification. 118# Internal flag not meant for direct setting. 119# Use BRANCH_PROTECTION to enable BTI. 120ENABLE_BTI := 0 121 122# Flag to enable Pointer Authentication. 123# Internal flag not meant for direct setting. 124# Use BRANCH_PROTECTION to enable PAUTH. 125ENABLE_PAUTH := 0 126 127# Flag to enable access to the HCRX_EL2 register by setting SCR_EL3.HXEn. 128ENABLE_FEAT_HCX := 0 129 130# By default BL31 encryption disabled 131ENCRYPT_BL31 := 0 132 133# By default BL32 encryption disabled 134ENCRYPT_BL32 := 0 135 136# Default dummy firmware encryption key 137ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef 138 139# Default dummy nonce for firmware encryption 140ENC_NONCE := 1234567890abcdef12345678 141 142# Build flag to treat usage of deprecated platform and framework APIs as error. 143ERROR_DEPRECATED := 0 144 145# Fault injection support 146FAULT_INJECTION_SUPPORT := 0 147 148# Byte alignment that each component in FIP is aligned to 149FIP_ALIGN := 0 150 151# Default FIP file name 152FIP_NAME := fip.bin 153 154# Default FWU_FIP file name 155FWU_FIP_NAME := fwu_fip.bin 156 157# By default firmware encryption with SSK 158FW_ENC_STATUS := 0 159 160# For Chain of Trust 161GENERATE_COT := 0 162 163# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 164# default, they are for Secure EL1. 165GICV2_G0_FOR_EL3 := 0 166 167# Route External Aborts to EL3. Disabled by default; External Aborts are handled 168# by lower ELs. 169HANDLE_EA_EL3_FIRST := 0 170 171# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. 172# The default value is sha256. 173HASH_ALG := sha256 174 175# Whether system coherency is managed in hardware, without explicit software 176# operations. 177HW_ASSISTED_COHERENCY := 0 178 179# Set the default algorithm for the generation of Trusted Board Boot keys 180KEY_ALG := rsa 181 182# Set the default key size in case KEY_ALG is rsa 183ifeq ($(KEY_ALG),rsa) 184KEY_SIZE := 2048 185endif 186 187# Option to build TF with Measured Boot support 188MEASURED_BOOT := 0 189 190# NS timer register save and restore 191NS_TIMER_SWITCH := 0 192 193# Include lib/libc in the final image 194OVERRIDE_LIBC := 0 195 196# Build PL011 UART driver in minimal generic UART mode 197PL011_GENERIC_UART := 0 198 199# By default, consider that the platform's reset address is not programmable. 200# The platform Makefile is free to override this value. 201PROGRAMMABLE_RESET_ADDRESS := 0 202 203# Flag used to choose the power state format: Extended State-ID or Original 204PSCI_EXTENDED_STATE_ID := 0 205 206# Enable RAS support 207RAS_EXTENSION := 0 208 209# By default, BL1 acts as the reset handler, not BL31 210RESET_TO_BL31 := 0 211 212# For Chain of Trust 213SAVE_KEYS := 0 214 215# Software Delegated Exception support 216SDEI_SUPPORT := 0 217 218# True Random Number firmware Interface 219TRNG_SUPPORT := 0 220 221# SMCCC PCI support 222SMC_PCI_SUPPORT := 0 223 224# Whether code and read-only data should be put on separate memory pages. The 225# platform Makefile is free to override this value. 226SEPARATE_CODE_AND_RODATA := 0 227 228# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 229# separate memory region, which may be discontiguous from the rest of BL31. 230SEPARATE_NOBITS_REGION := 0 231 232# If the BL31 image initialisation code is recalimed after use for the secondary 233# cores stack 234RECLAIM_INIT_CODE := 0 235 236# SPD choice 237SPD := none 238 239# Enable the Management Mode (MM)-based Secure Partition Manager implementation 240SPM_MM := 0 241 242# Use SPM at S-EL2 as a default config for SPMD 243SPMD_SPM_AT_SEL2 := 1 244 245# Flag to introduce an infinite loop in BL1 just before it exits into the next 246# image. This is meant to help debugging the post-BL2 phase. 247SPIN_ON_BL1_EXIT := 0 248 249# Flags to build TF with Trusted Boot support 250TRUSTED_BOARD_BOOT := 0 251 252# Build option to choose whether Trusted Firmware uses Coherent memory or not. 253USE_COHERENT_MEM := 1 254 255# Build option to add debugfs support 256USE_DEBUGFS := 0 257 258# Build option to fconf based io 259ARM_IO_IN_DTB := 0 260 261# Build option to support SDEI through fconf 262SDEI_IN_FCONF := 0 263 264# Build option to support Secure Interrupt descriptors through fconf 265SEC_INT_DESC_IN_FCONF := 0 266 267# Build option to choose whether Trusted Firmware uses library at ROM 268USE_ROMLIB := 0 269 270# Build option to choose whether the xlat tables of BL images can be read-only. 271# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES, 272# which is the per BL-image option that actually enables the read-only tables 273# API. The reason for having this additional option is to have a common high 274# level makefile where we can check for incompatible features/build options. 275ALLOW_RO_XLAT_TABLES := 0 276 277# Chain of trust. 278COT := tbbr 279 280# Use tbbr_oid.h instead of platform_oid.h 281USE_TBBR_DEFS := 1 282 283# Build verbosity 284V := 0 285 286# Whether to enable D-Cache early during warm boot. This is usually 287# applicable for platforms wherein interconnect programming is not 288# required to enable cache coherency after warm reset (eg: single cluster 289# platforms). 290WARMBOOT_ENABLE_DCACHE_EARLY := 0 291 292# Build option to enable/disable the Statistical Profiling Extensions 293ENABLE_SPE_FOR_LOWER_ELS := 1 294 295# SPE is only supported on AArch64 so disable it on AArch32. 296ifeq (${ARCH},aarch32) 297 override ENABLE_SPE_FOR_LOWER_ELS := 0 298endif 299 300# Include Memory Tagging Extension registers in cpu context. This must be set 301# to 1 if the platform wants to use this feature in the Secure world and MTE is 302# enabled at ELX. 303CTX_INCLUDE_MTE_REGS := 0 304 305ENABLE_AMU := 0 306AMU_RESTRICT_COUNTERS := 0 307 308# By default, enable Scalable Vector Extension if implemented only for Non-secure 309# lower ELs 310# Note SVE is only supported on AArch64 - therefore do not enable in AArch32 311ifneq (${ARCH},aarch32) 312 ENABLE_SVE_FOR_NS := 1 313 ENABLE_SVE_FOR_SWD := 0 314else 315 override ENABLE_SVE_FOR_NS := 0 316 override ENABLE_SVE_FOR_SWD := 0 317endif 318 319SANITIZE_UB := off 320 321# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock 322# implementation variant using the ARMv8.1-LSE compare-and-swap instruction. 323# Default: disabled 324USE_SPINLOCK_CAS := 0 325 326# Enable Link Time Optimization 327ENABLE_LTO := 0 328 329# Build flag to include EL2 registers in cpu context save and restore during 330# S-EL2 firmware entry/exit. This flag is to be used with SPD=spmd option. 331# Default is 0. 332CTX_INCLUDE_EL2_REGS := 0 333 334# Enable Memory tag extension which is supported for architecture greater 335# than Armv8.5-A 336# By default it is set to "no" 337SUPPORT_STACK_MEMTAG := no 338 339# Select workaround for AT speculative behaviour. 340ERRATA_SPECULATIVE_AT := 0 341 342# Trap RAS error record access from lower EL 343RAS_TRAP_LOWER_EL_ERR_ACCESS := 0 344 345# Build option to create cot descriptors using fconf 346COT_DESC_IN_DTB := 0 347 348# Build option to provide openssl directory path 349OPENSSL_DIR := /usr 350 351# Build option to use the SP804 timer instead of the generic one 352USE_SP804_TIMER := 0 353 354# Build option to define number of firmware banks, used in firmware update 355# metadata structure. 356NR_OF_FW_BANKS := 2 357 358# Build option to define number of images in firmware bank, used in firmware 359# update metadata structure. 360NR_OF_IMAGES_IN_FW_BANK := 1 361 362# Disable Firmware update support by default 363PSA_FWU_SUPPORT := 0 364 365# By default, disable access of trace buffer control registers from NS 366# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused 367# if FEAT_TRBE is implemented. 368# Note FEAT_TRBE is only supported on AArch64 - therefore do not enable in 369# AArch32. 370ifneq (${ARCH},aarch32) 371 ENABLE_TRBE_FOR_NS := 0 372else 373 override ENABLE_TRBE_FOR_NS := 0 374endif 375 376# By default, disable access of trace system registers from NS lower 377# ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused if 378# system register trace is implemented. 379ENABLE_SYS_REG_TRACE_FOR_NS := 0 380 381# By default, disable trace filter control registers access to NS 382# lower ELs, i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused 383# if FEAT_TRF is implemented. 384ENABLE_TRF_FOR_NS := 0 385