1/* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <context.h> 13#include <lib/xlat_tables/xlat_tables_defs.h> 14 15 /* 16 * Helper macro to initialise EL3 registers we care about. 17 */ 18 .macro el3_arch_init_common 19 /* --------------------------------------------------------------------- 20 * SCTLR_EL3 has already been initialised - read current value before 21 * modifying. 22 * 23 * SCTLR_EL3.I: Enable the instruction cache. 24 * 25 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault 26 * exception is generated if a load or store instruction executed at 27 * EL3 uses the SP as the base address and the SP is not aligned to a 28 * 16-byte boundary. 29 * 30 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that 31 * load or store one or more registers have an alignment check that the 32 * address being accessed is aligned to the size of the data element(s) 33 * being accessed. 34 * --------------------------------------------------------------------- 35 */ 36 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 37 mrs x0, sctlr_el3 38 orr x0, x0, x1 39 msr sctlr_el3, x0 40 isb 41 42#ifdef IMAGE_BL31 43 /* --------------------------------------------------------------------- 44 * Initialise the per-cpu cache pointer to the CPU. 45 * This is done early to enable crash reporting to have access to crash 46 * stack. Since crash reporting depends on cpu_data to report the 47 * unhandled exception, not doing so can lead to recursive exceptions 48 * due to a NULL TPIDR_EL3. 49 * --------------------------------------------------------------------- 50 */ 51 bl init_cpu_data_ptr 52#endif /* IMAGE_BL31 */ 53 54 /* --------------------------------------------------------------------- 55 * Initialise SCR_EL3, setting all fields rather than relying on hw. 56 * All fields are architecturally UNKNOWN on reset. The following fields 57 * do not change during the TF lifetime. The remaining fields are set to 58 * zero here but are updated ahead of transitioning to a lower EL in the 59 * function cm_init_context_common(). 60 * 61 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 62 * EL2, EL1 and EL0 are not trapped to EL3. 63 * 64 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 65 * EL2, EL1 and EL0 are not trapped to EL3. 66 * 67 * SCR_EL3.SIF: Set to one to disable instruction fetches from 68 * Non-secure memory. 69 * 70 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 71 * both Security states and both Execution states. 72 * 73 * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts 74 * to EL3 when executing at any EL. 75 * 76 * SCR_EL3.{API,APK}: For Armv8.3 pointer authentication feature, 77 * disable traps to EL3 when accessing key registers or using pointer 78 * authentication instructions from lower ELs. 79 * --------------------------------------------------------------------- 80 */ 81 mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) \ 82 & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT)) 83#if CTX_INCLUDE_PAUTH_REGS 84 /* 85 * If the pointer authentication registers are saved during world 86 * switches, enable pointer authentication everywhere, as it is safe to 87 * do so. 88 */ 89 orr x0, x0, #(SCR_API_BIT | SCR_APK_BIT) 90#endif 91 msr scr_el3, x0 92 93 /* --------------------------------------------------------------------- 94 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 95 * Some fields are architecturally UNKNOWN on reset. 96 * 97 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 98 * Debug exceptions, other than Breakpoint Instruction exceptions, are 99 * disabled from all ELs in Secure state. 100 * 101 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 102 * privileged debug from S-EL1. 103 * 104 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 105 * access to the powerdown debug registers do not trap to EL3. 106 * 107 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 108 * debug registers, other than those registers that are controlled by 109 * MDCR_EL3.TDOSA. 110 * 111 * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register 112 * accesses to all Performance Monitors registers do not trap to EL3. 113 * 114 * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is 115 * prohibited in Secure state. This bit is RES0 in versions of the 116 * architecture with FEAT_PMUv3p5 not implemented, setting it to 1 117 * doesn't have any effect on them. 118 * 119 * MDCR_EL3.MCCD: Set to one so that cycle counting by PMCCNTR_EL0 is 120 * prohibited in EL3. This bit is RES0 in versions of the 121 * architecture with FEAT_PMUv3p7 not implemented, setting it to 1 122 * doesn't have any effect on them. 123 * 124 * MDCR_EL3.SPME: Set to zero so that event counting by the programmable 125 * counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If ARMv8.2 126 * Debug is not implemented this bit does not have any effect on the 127 * counters unless there is support for the implementation defined 128 * authentication interface ExternalSecureNoninvasiveDebugEnabled(). 129 * 130 * MDCR_EL3.NSTB, MDCR_EL3.NSTBE: Set to zero so that Trace Buffer 131 * owning security state is Secure state. If FEAT_TRBE is implemented, 132 * accesses to Trace Buffer control registers at EL2 and EL1 in any 133 * security state generates trap exceptions to EL3. 134 * If FEAT_TRBE is not implemented, these bits are RES0. 135 * --------------------------------------------------------------------- 136 */ 137 mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ 138 MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT | \ 139 MDCR_MCCD_BIT) & ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | \ 140 MDCR_TDA_BIT | MDCR_TPM_BIT | MDCR_NSTB(MDCR_NSTB_EL1) | \ 141 MDCR_NSTBE)) 142 143 msr mdcr_el3, x0 144 145 /* --------------------------------------------------------------------- 146 * Initialise PMCR_EL0 setting all fields rather than relying 147 * on hw. Some fields are architecturally UNKNOWN on reset. 148 * 149 * PMCR_EL0.LP: Set to one so that event counter overflow, that 150 * is recorded in PMOVSCLR_EL0[0-30], occurs on the increment 151 * that changes PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU 152 * is implemented. This bit is RES0 in versions of the architecture 153 * earlier than ARMv8.5, setting it to 1 doesn't have any effect 154 * on them. 155 * 156 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that 157 * is recorded in PMOVSCLR_EL0[31], occurs on the increment 158 * that changes PMCCNTR_EL0[63] from 1 to 0. 159 * 160 * PMCR_EL0.DP: Set to one so that the cycle counter, 161 * PMCCNTR_EL0 does not count when event counting is prohibited. 162 * 163 * PMCR_EL0.X: Set to zero to disable export of events. 164 * 165 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 166 * counts on every clock cycle. 167 * --------------------------------------------------------------------- 168 */ 169 mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_LP_BIT | \ 170 PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT) & \ 171 ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)) 172 173 msr pmcr_el0, x0 174 175 /* --------------------------------------------------------------------- 176 * Enable External Aborts and SError Interrupts now that the exception 177 * vectors have been setup. 178 * --------------------------------------------------------------------- 179 */ 180 msr daifclr, #DAIF_ABT_BIT 181 182 /* --------------------------------------------------------------------- 183 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 184 * All fields are architecturally UNKNOWN on reset. 185 * 186 * CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1, 187 * CPTR_EL2, CPACR, or HCPTR do not trap to EL3. 188 * 189 * CPTR_EL3.TTA: Set to one so that accesses to the trace system 190 * registers trap to EL3 from all exception levels and security 191 * states when system register trace is implemented. 192 * When system register trace is not implemented, this bit is RES0 and 193 * hence set to zero. 194 * 195 * CPTR_EL3.TTA: Set to zero so that System register accesses to the 196 * trace registers do not trap to EL3. 197 * 198 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 199 * by Advanced SIMD, floating-point or SVE instructions (if implemented) 200 * do not trap to EL3. 201 * 202 * CPTR_EL3.TAM: Set to one so that Activity Monitor access is 203 * trapped to EL3 by default. 204 * 205 * CPTR_EL3.EZ: Set to zero so that all SVE functionality is trapped 206 * to EL3 by default. 207 */ 208 209 mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT)) 210 mrs x1, id_aa64dfr0_el1 211 ubfx x1, x1, #ID_AA64DFR0_TRACEVER_SHIFT, #ID_AA64DFR0_TRACEVER_LENGTH 212 cbz x1, 1f 213 orr x0, x0, #TTA_BIT 2141: 215 msr cptr_el3, x0 216 217 /* 218 * If Data Independent Timing (DIT) functionality is implemented, 219 * always enable DIT in EL3 220 */ 221 mrs x0, id_aa64pfr0_el1 222 ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH 223 cmp x0, #ID_AA64PFR0_DIT_SUPPORTED 224 bne 1f 225 mov x0, #DIT_BIT 226 msr DIT, x0 2271: 228 .endm 229 230/* ----------------------------------------------------------------------------- 231 * This is the super set of actions that need to be performed during a cold boot 232 * or a warm boot in EL3. This code is shared by BL1 and BL31. 233 * 234 * This macro will always perform reset handling, architectural initialisations 235 * and stack setup. The rest of the actions are optional because they might not 236 * be needed, depending on the context in which this macro is called. This is 237 * why this macro is parameterised ; each parameter allows to enable/disable 238 * some actions. 239 * 240 * _init_sctlr: 241 * Whether the macro needs to initialise SCTLR_EL3, including configuring 242 * the endianness of data accesses. 243 * 244 * _warm_boot_mailbox: 245 * Whether the macro needs to detect the type of boot (cold/warm). The 246 * detection is based on the platform entrypoint address : if it is zero 247 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 248 * this macro jumps on the platform entrypoint address. 249 * 250 * _secondary_cold_boot: 251 * Whether the macro needs to identify the CPU that is calling it: primary 252 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 253 * the platform initialisations, while the secondaries will be put in a 254 * platform-specific state in the meantime. 255 * 256 * If the caller knows this macro will only be called by the primary CPU 257 * then this parameter can be defined to 0 to skip this step. 258 * 259 * _init_memory: 260 * Whether the macro needs to initialise the memory. 261 * 262 * _init_c_runtime: 263 * Whether the macro needs to initialise the C runtime environment. 264 * 265 * _exception_vectors: 266 * Address of the exception vectors to program in the VBAR_EL3 register. 267 * 268 * _pie_fixup_size: 269 * Size of memory region to fixup Global Descriptor Table (GDT). 270 * 271 * A non-zero value is expected when firmware needs GDT to be fixed-up. 272 * 273 * ----------------------------------------------------------------------------- 274 */ 275 .macro el3_entrypoint_common \ 276 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 277 _init_memory, _init_c_runtime, _exception_vectors, \ 278 _pie_fixup_size 279 280 .if \_init_sctlr 281 /* ------------------------------------------------------------- 282 * This is the initialisation of SCTLR_EL3 and so must ensure 283 * that all fields are explicitly set rather than relying on hw. 284 * Some fields reset to an IMPLEMENTATION DEFINED value and 285 * others are architecturally UNKNOWN on reset. 286 * 287 * SCTLR.EE: Set the CPU endianness before doing anything that 288 * might involve memory reads or writes. Set to zero to select 289 * Little Endian. 290 * 291 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can 292 * force all memory regions that are writeable to be treated as 293 * XN (Execute-never). Set to zero so that this control has no 294 * effect on memory access permissions. 295 * 296 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check. 297 * 298 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking. 299 * 300 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 301 * safe behaviour upon exception entry to EL3. 302 * ------------------------------------------------------------- 303 */ 304 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ 305 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) 306 msr sctlr_el3, x0 307 isb 308 .endif /* _init_sctlr */ 309 310#if DISABLE_MTPMU 311 bl mtpmu_disable 312#endif 313 314 .if \_warm_boot_mailbox 315 /* ------------------------------------------------------------- 316 * This code will be executed for both warm and cold resets. 317 * Now is the time to distinguish between the two. 318 * Query the platform entrypoint address and if it is not zero 319 * then it means it is a warm boot so jump to this address. 320 * ------------------------------------------------------------- 321 */ 322 bl plat_get_my_entrypoint 323 cbz x0, do_cold_boot 324 br x0 325 326 do_cold_boot: 327 .endif /* _warm_boot_mailbox */ 328 329 .if \_pie_fixup_size 330#if ENABLE_PIE 331 /* 332 * ------------------------------------------------------------ 333 * If PIE is enabled fixup the Global descriptor Table only 334 * once during primary core cold boot path. 335 * 336 * Compile time base address, required for fixup, is calculated 337 * using "pie_fixup" label present within first page. 338 * ------------------------------------------------------------ 339 */ 340 pie_fixup: 341 ldr x0, =pie_fixup 342 and x0, x0, #~(PAGE_SIZE_MASK) 343 mov_imm x1, \_pie_fixup_size 344 add x1, x1, x0 345 bl fixup_gdt_reloc 346#endif /* ENABLE_PIE */ 347 .endif /* _pie_fixup_size */ 348 349 /* --------------------------------------------------------------------- 350 * Set the exception vectors. 351 * --------------------------------------------------------------------- 352 */ 353 adr x0, \_exception_vectors 354 msr vbar_el3, x0 355 isb 356 357 /* --------------------------------------------------------------------- 358 * It is a cold boot. 359 * Perform any processor specific actions upon reset e.g. cache, TLB 360 * invalidations etc. 361 * --------------------------------------------------------------------- 362 */ 363 bl reset_handler 364 365 el3_arch_init_common 366 367 .if \_secondary_cold_boot 368 /* ------------------------------------------------------------- 369 * Check if this is a primary or secondary CPU cold boot. 370 * The primary CPU will set up the platform while the 371 * secondaries are placed in a platform-specific state until the 372 * primary CPU performs the necessary actions to bring them out 373 * of that state and allows entry into the OS. 374 * ------------------------------------------------------------- 375 */ 376 bl plat_is_my_cpu_primary 377 cbnz w0, do_primary_cold_boot 378 379 /* This is a cold boot on a secondary CPU */ 380 bl plat_secondary_cold_boot_setup 381 /* plat_secondary_cold_boot_setup() is not supposed to return */ 382 bl el3_panic 383 384 do_primary_cold_boot: 385 .endif /* _secondary_cold_boot */ 386 387 /* --------------------------------------------------------------------- 388 * Initialize memory now. Secondary CPU initialization won't get to this 389 * point. 390 * --------------------------------------------------------------------- 391 */ 392 393 .if \_init_memory 394 bl platform_mem_init 395 .endif /* _init_memory */ 396 397 /* --------------------------------------------------------------------- 398 * Init C runtime environment: 399 * - Zero-initialise the NOBITS sections. There are 2 of them: 400 * - the .bss section; 401 * - the coherent memory section (if any). 402 * - Relocate the data section from ROM to RAM, if required. 403 * --------------------------------------------------------------------- 404 */ 405 .if \_init_c_runtime 406#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_INV_DCACHE) 407 /* ------------------------------------------------------------- 408 * Invalidate the RW memory used by the BL31 image. This 409 * includes the data and NOBITS sections. This is done to 410 * safeguard against possible corruption of this memory by 411 * dirty cache lines in a system cache as a result of use by 412 * an earlier boot loader stage. 413 * ------------------------------------------------------------- 414 */ 415 adrp x0, __RW_START__ 416 add x0, x0, :lo12:__RW_START__ 417 adrp x1, __RW_END__ 418 add x1, x1, :lo12:__RW_END__ 419 sub x1, x1, x0 420 bl inv_dcache_range 421#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION 422 adrp x0, __NOBITS_START__ 423 add x0, x0, :lo12:__NOBITS_START__ 424 adrp x1, __NOBITS_END__ 425 add x1, x1, :lo12:__NOBITS_END__ 426 sub x1, x1, x0 427 bl inv_dcache_range 428#endif 429#endif 430 adrp x0, __BSS_START__ 431 add x0, x0, :lo12:__BSS_START__ 432 433 adrp x1, __BSS_END__ 434 add x1, x1, :lo12:__BSS_END__ 435 sub x1, x1, x0 436 bl zeromem 437 438#if USE_COHERENT_MEM 439 adrp x0, __COHERENT_RAM_START__ 440 add x0, x0, :lo12:__COHERENT_RAM_START__ 441 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 442 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__ 443 sub x1, x1, x0 444 bl zeromem 445#endif 446 447#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM) 448 adrp x0, __DATA_RAM_START__ 449 add x0, x0, :lo12:__DATA_RAM_START__ 450 adrp x1, __DATA_ROM_START__ 451 add x1, x1, :lo12:__DATA_ROM_START__ 452 adrp x2, __DATA_RAM_END__ 453 add x2, x2, :lo12:__DATA_RAM_END__ 454 sub x2, x2, x0 455 bl memcpy16 456#endif 457 .endif /* _init_c_runtime */ 458 459 /* --------------------------------------------------------------------- 460 * Use SP_EL0 for the C runtime stack. 461 * --------------------------------------------------------------------- 462 */ 463 msr spsel, #0 464 465 /* --------------------------------------------------------------------- 466 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 467 * the MMU is enabled. There is no risk of reading stale stack memory 468 * after enabling the MMU as only the primary CPU is running at the 469 * moment. 470 * --------------------------------------------------------------------- 471 */ 472 bl plat_set_my_stack 473 474#if STACK_PROTECTOR_ENABLED 475 .if \_init_c_runtime 476 bl update_stack_protector_canary 477 .endif /* _init_c_runtime */ 478#endif 479 .endm 480 481 .macro apply_at_speculative_wa 482#if ERRATA_SPECULATIVE_AT 483 /* 484 * Explicitly save x30 so as to free up a register and to enable 485 * branching and also, save x29 which will be used in the called 486 * function 487 */ 488 stp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 489 bl save_and_update_ptw_el1_sys_regs 490 ldp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 491#endif 492 .endm 493 494 .macro restore_ptw_el1_sys_regs 495#if ERRATA_SPECULATIVE_AT 496 /* ----------------------------------------------------------- 497 * In case of ERRATA_SPECULATIVE_AT, must follow below order 498 * to ensure that page table walk is not enabled until 499 * restoration of all EL1 system registers. TCR_EL1 register 500 * should be updated at the end which restores previous page 501 * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB 502 * ensures that CPU does below steps in order. 503 * 504 * 1. Ensure all other system registers are written before 505 * updating SCTLR_EL1 using ISB. 506 * 2. Restore SCTLR_EL1 register. 507 * 3. Ensure SCTLR_EL1 written successfully using ISB. 508 * 4. Restore TCR_EL1 register. 509 * ----------------------------------------------------------- 510 */ 511 isb 512 ldp x28, x29, [sp, #CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1] 513 msr sctlr_el1, x28 514 isb 515 msr tcr_el1, x29 516#endif 517 .endm 518 519#endif /* EL3_COMMON_MACROS_S */ 520