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Searched refs:gpll_hz (Results 1 – 25 of 31) sorted by relevance

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/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rv1126.c232 return DIV_TO_RATE(priv->gpll_hz, div); in rv1126_i2c_get_pmuclk()
241 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_i2c_set_pmuclk()
285 return DIV_TO_RATE(priv->gpll_hz, div); in rv1126_pwm_get_pmuclk()
303 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pwm_set_pmuclk()
321 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pwm_set_pmuclk()
346 return DIV_TO_RATE(priv->gpll_hz, div); in rv1126_spi_get_pmuclk()
355 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_spi_set_pmuclk()
374 return DIV_TO_RATE(priv->gpll_hz, div); in rv1126_pdpmu_get_pmuclk()
383 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdpmu_set_pmuclk()
398 if (!priv->gpll_hz) { in rv1126_pmuclk_get_rate()
[all …]
H A Dclk_px30.c324 return DIV_TO_RATE(priv->gpll_hz, div); in px30_i2c_get_clk()
332 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_i2c_set_clk()
527 return DIV_TO_RATE(priv->gpll_hz, div); in px30_nandc_get_clk()
538 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); in px30_nandc_set_clk()
577 return DIV_TO_RATE(priv->gpll_hz, div) / 2; in px30_mmc_get_clk()
603 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); in px30_mmc_set_clk()
632 return DIV_TO_RATE(priv->gpll_hz, div); in px30_sfc_get_clk()
641 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); in px30_sfc_set_clk()
669 return DIV_TO_RATE(priv->gpll_hz, div); in px30_pwm_get_clk()
677 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_pwm_set_clk()
[all …]
H A Dclk_rk1808.c130 return DIV_TO_RATE(priv->gpll_hz, div); in rk1808_i2c_get_clk()
139 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_i2c_set_clk()
218 return DIV_TO_RATE(priv->gpll_hz, div) / 2; in rk1808_mmc_get_clk()
247 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); in rk1808_mmc_set_clk()
276 return DIV_TO_RATE(priv->gpll_hz, div); in rk1808_sfc_get_clk()
285 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); in rk1808_sfc_set_clk()
344 return DIV_TO_RATE(priv->gpll_hz, div); in rk1808_pwm_get_clk()
353 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_pwm_set_clk()
432 return DIV_TO_RATE(priv->gpll_hz, div); in rk1808_spi_get_clk()
441 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_spi_set_clk()
[all …]
H A Dclk_rk3506.c196 prate = priv->gpll_hz; in rk3506_armclk_get_rate()
241 div = DIV_ROUND_UP(priv->gpll_hz, new_rate); in rk3506_armclk_set_rate()
242 prate = priv->gpll_hz; in rk3506_armclk_set_rate()
280 prate = priv->gpll_hz; in rk3506_pll_div_get_rate()
312 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3506_pll_div_set_rate()
508 prate = priv->gpll_hz; in rk3506_sdmmc_get_rate()
536 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3506_sdmmc_set_rate()
668 prate = priv->gpll_hz; in rk3506_i2c_get_rate()
693 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3506_i2c_set_rate()
880 prate = priv->gpll_hz; in rk3506_fspi_get_rate()
[all …]
H A Dclk_rk3576.c184 rate = DIV_TO_RATE(priv->gpll_hz, div); in rk3576_bus_get_clk()
230 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3576_bus_set_clk()
292 prate = priv->gpll_hz; in rk3576_top_get_clk()
303 prate = priv->gpll_hz; in rk3576_top_get_clk()
347 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3576_top_set_clk()
363 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3576_top_set_clk()
705 prate = priv->gpll_hz; in rk3576_adc_get_clk()
737 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3576_adc_set_clk()
775 prate = priv->gpll_hz; in rk3576_mmc_get_clk()
788 prate = priv->gpll_hz; in rk3576_mmc_get_clk()
[all …]
H A Dclk_rv1103b.c93 rate = DIV_TO_RATE(priv->gpll_hz, 11); in rv1103b_peri_get_clk()
287 prate = priv->gpll_hz; in rv1103b_mmc_get_clk()
299 prate = priv->gpll_hz; in rv1103b_mmc_get_clk()
311 prate = priv->gpll_hz; in rv1103b_mmc_get_clk()
323 prate = priv->gpll_hz; in rv1103b_mmc_get_clk()
344 prate = priv->gpll_hz; in rv1103b_mmc_set_clk()
690 p_rate = priv->gpll_hz; in rv1103b_uart_get_rate()
712 if (priv->gpll_hz % rate == 0) { in rv1103b_uart_set_rate()
714 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1103b_uart_set_rate()
721 rational_best_approximation(rate, priv->gpll_hz / div, in rv1103b_uart_set_rate()
[all …]
H A Dclk_rk3328.c194 return DIV_TO_RATE(priv->gpll_hz, div); in rk3328_i2c_get_clk()
203 src_clk_div = priv->gpll_hz / hz; in rk3328_i2c_set_clk()
240 return DIV_TO_RATE(priv->gpll_hz, src_clk_div); in rk3328_i2c_set_clk()
265 pll_rate = priv->gpll_hz; in rk3328_gmac2io_set_clk()
341 return DIV_TO_RATE(priv->gpll_hz, div) / 2; in rk3328_mmc_get_clk()
365 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); in rk3328_mmc_set_clk()
393 p_rate = priv->gpll_hz; in rk3328_spi_get_clk()
403 u32 div = priv->gpll_hz / hz; in rk3328_spi_set_clk()
410 return DIV_TO_RATE(priv->gpll_hz, div); in rk3328_spi_set_clk()
422 return DIV_TO_RATE(priv->gpll_hz, div); in rk3328_pwm_get_clk()
[all …]
H A Dclk_rk322x.c175 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : priv->gpll_hz; in rk322x_mmc_get_clk()
198 pll_rate = priv->gpll_hz; in rk322x_mac_set_clk()
225 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, freq); in rk322x_mmc_set_clk()
279 parent = priv->gpll_hz; in rk322x_bus_get_clk()
315 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk322x_bus_set_clk()
357 parent = priv->gpll_hz; in rk322x_peri_get_clk()
388 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk322x_peri_set_clk()
428 parent = priv->gpll_hz; in rk322x_spi_get_clk()
438 div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk322x_spi_set_clk()
457 parent = priv->gpll_hz; in rk322x_vop_get_clk()
[all …]
H A Dclk_rk3588.c298 prate = priv->gpll_hz; in rk3588_top_get_clk()
309 prate = priv->gpll_hz; in rk3588_top_get_clk()
341 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_top_set_clk()
352 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_top_set_clk()
667 prate = priv->gpll_hz; in rk3588_adc_get_clk()
704 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_adc_set_clk()
727 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_adc_set_clk()
756 prate = priv->gpll_hz; in rk3588_mmc_get_clk()
768 prate = priv->gpll_hz; in rk3588_mmc_get_clk()
782 prate = priv->gpll_hz; in rk3588_mmc_get_clk()
[all …]
H A Dclk_rk3562.c231 rate = priv->gpll_hz; in rk3562_bus_get_rate()
247 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_bus_set_rate()
305 rate = priv->gpll_hz; in rk3562_peri_get_rate()
321 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_peri_set_rate()
504 p_rate = priv->gpll_hz; in rk3562_uart_get_rate()
587 if (priv->gpll_hz % rate == 0) { in rk3562_uart_set_rate()
590 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_uart_set_rate()
603 rational_best_approximation(rate, priv->gpll_hz / div, in rk3562_uart_set_rate()
924 parent = priv->gpll_hz; in rk3562_sfc_get_rate()
945 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_sfc_set_rate()
[all …]
H A Dclk_rk3528.c415 prate = priv->gpll_hz; in rk3528_cgpll_matrix_get_rate()
420 prate = priv->gpll_hz; in rk3528_cgpll_matrix_get_rate()
521 if (priv->gpll_hz % rate == 0) { in rk3528_cgpll_matrix_set_rate()
523 prate = priv->gpll_hz; in rk3528_cgpll_matrix_set_rate()
530 prate = priv->gpll_hz; in rk3528_cgpll_matrix_set_rate()
919 prate = priv->gpll_hz; in rk3528_sdmmc_get_clk()
941 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3528_sdmmc_set_clk()
966 parent = priv->gpll_hz; in rk3528_sfc_get_clk()
987 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3528_sfc_set_clk()
1013 parent = priv->gpll_hz; in rk3528_emmc_get_clk()
[all …]
H A Dclk_rk3128.c173 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : priv->gpll_hz; in rockchip_mmc_get_clk()
185 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, freq); in rockchip_mmc_set_clk()
232 parent = priv->gpll_hz; in rk3128_peri_get_clk()
266 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk3128_peri_set_clk()
313 parent = priv->gpll_hz; in rk3128_bus_get_clk()
341 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk3128_bus_set_clk()
381 parent = priv->gpll_hz; in rk3128_spi_get_clk()
391 div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk3128_spi_set_clk()
607 priv->gpll_hz = rate; in rk3128_clk_set_rate()
814 priv->gpll_hz = rockchip_pll_get_rate(&rk3128_pll_clks[GPLL], in rkclk_init()
[all …]
H A Dclk_rv1126b.c365 prate = priv->gpll_hz; in rv1126b_mmc_get_clk()
379 prate = priv->gpll_hz; in rv1126b_mmc_get_clk()
393 prate = priv->gpll_hz; in rv1126b_mmc_get_clk()
408 prate = priv->gpll_hz; in rv1126b_mmc_get_clk()
449 prate = priv->gpll_hz; in rv1126b_mmc_set_clk()
891 p_rate = priv->gpll_hz; in rv1126b_frac_get_rate()
934 p_rate = priv->gpll_hz; in rv1126b_frac_set_rate()
1339 p_rate = priv->gpll_hz; in rv1126b_vop_get_rate()
1355 p_rate = priv->gpll_hz; in rv1126b_vop_set_rate()
1399 p_rate = priv->gpll_hz; in rv1126b_mac_get_rate()
[all …]
H A Dclk_rv1106.c839 p_rate = priv->gpll_hz; in rv1106_uart_get_rate()
865 if (priv->gpll_hz % rate == 0) { in rv1106_uart_set_rate()
868 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1106_uart_set_rate()
872 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1106_uart_set_rate()
881 rational_best_approximation(rate, priv->gpll_hz / div, in rv1106_uart_set_rate()
949 return DIV_TO_RATE(priv->gpll_hz, div); in rv1106_vop_get_clk()
985 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1106_vop_set_clk()
1044 if (!priv->gpll_hz) { in rv1106_clk_get_rate()
1045 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); in rv1106_clk_get_rate()
1149 if (!priv->gpll_hz) { in rv1106_clk_set_rate()
[all …]
H A Dclk_rk3568.c1749 parent = priv->gpll_hz; in rk3568_aclk_vop_get_clk()
1769 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3568_aclk_vop_set_clk()
1809 parent = priv->gpll_hz; in rk3568_dclk_vop_get_clk()
1865 pll_rate = priv->gpll_hz; in rk3568_dclk_vop_set_clk()
2146 p_rate = priv->gpll_hz; in rk3568_rkvdec_get_clk()
2161 p_rate = priv->gpll_hz; in rk3568_rkvdec_get_clk()
2182 p_rate = priv->gpll_hz; in rk3568_rkvdec_set_clk()
2201 p_rate = priv->gpll_hz; in rk3568_rkvdec_set_clk()
2260 p_rate = priv->gpll_hz; in rk3568_uart_get_rate()
2286 if (priv->gpll_hz % rate == 0) { in rk3568_uart_set_rate()
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rv1126.h65 ulong gpll_hz; member
71 ulong gpll_hz; member
H A Dcru_px30.h44 ulong gpll_hz; member
54 ulong gpll_hz; member
H A Dcru_rk3128.h24 ulong gpll_hz; member
H A Dcru_rk322x.h22 ulong gpll_hz; member
H A Dcru_rk3328.h16 ulong gpll_hz; member
H A Dcru_rv1103b.h34 ulong gpll_hz; member
H A Dcru_rv1106.h42 ulong gpll_hz; member
H A Dcru_rk3506.h32 ulong gpll_hz; member
H A Dcru_rk1808.h40 ulong gpll_hz; member
/rk3399_rockchip-uboot/drivers/spi/
H A Drk_spi.c255 const unsigned long gpll_hz = 594000000UL; in rockchip_spi_calc_modclk() local
268 div = DIV_ROUND_UP(gpll_hz, max_freq * 4); in rockchip_spi_calc_modclk()
269 return gpll_hz / div; in rockchip_spi_calc_modclk()

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