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Searched refs:cpll_hz (Results 1 – 22 of 22) sorted by relevance

/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3576.c182 rate = DIV_TO_RATE(priv->cpll_hz , div); in rk3576_bus_get_clk()
225 if (!(priv->cpll_hz % rate)) { in rk3576_bus_set_clk()
227 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3576_bus_set_clk()
288 prate = priv->cpll_hz; in rk3576_top_get_clk()
301 prate = priv->cpll_hz; in rk3576_top_get_clk()
342 if (!(priv->cpll_hz % rate)) { in rk3576_top_set_clk()
344 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3576_top_set_clk()
358 if (!(priv->cpll_hz % rate)) { in rk3576_top_set_clk()
360 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3576_top_set_clk()
777 prate = priv->cpll_hz; in rk3576_mmc_get_clk()
[all …]
H A Dclk_rk3562.c229 rate = priv->cpll_hz; in rk3562_bus_get_rate()
242 if (priv->cpll_hz % rate == 0) { in rk3562_bus_set_rate()
244 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_bus_set_rate()
303 rate = priv->cpll_hz; in rk3562_peri_get_rate()
316 if (priv->cpll_hz % rate == 0) { in rk3562_peri_set_rate()
318 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_peri_set_rate()
458 return DIV_TO_RATE(priv->cpll_hz, div); in rk3562_uart_get_rate()
465 return DIV_TO_RATE(priv->cpll_hz, div) * n / m; in rk3562_uart_get_rate()
506 p_rate = priv->cpll_hz; in rk3562_uart_get_rate()
530 if (priv->cpll_hz % rate == 0) { in rk3562_uart_set_rate()
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H A Dclk_rv1126b.c367 prate = priv->cpll_hz; in rv1126b_mmc_get_clk()
381 prate = priv->cpll_hz; in rv1126b_mmc_get_clk()
395 prate = priv->cpll_hz; in rv1126b_mmc_get_clk()
410 prate = priv->cpll_hz; in rv1126b_mmc_get_clk()
444 } else if ((priv->cpll_hz % rate) == 0) { in rv1126b_mmc_set_clk()
446 prate = priv->cpll_hz; in rv1126b_mmc_set_clk()
503 prate = priv->cpll_hz; in rv1126b_mmc_set_clk()
658 prate = priv->cpll_hz; in rv1126b_pwm_set_clk()
897 p_rate = priv->cpll_hz; in rv1126b_frac_get_rate()
929 } else if ((priv->cpll_hz % rate) == 0) { in rv1126b_frac_set_rate()
[all …]
H A Dclk_rk3328.c267 pll_rate = priv->cpll_hz; in rk3328_gmac2io_set_clk()
395 p_rate = priv->cpll_hz; in rk3328_spi_get_clk()
502 parent = priv->cpll_hz; in rk3328_vop_get_clk()
508 parent = priv->cpll_hz; in rk3328_vop_get_clk()
530 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz); in rk3328_vop_set_clk()
565 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz); in rk3328_vop_set_clk()
593 parent = priv->cpll_hz; in rk3328_bus_get_clk()
624 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz); in rk3328_bus_set_clk()
667 parent = priv->cpll_hz; in rk3328_peri_get_clk()
698 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz); in rk3328_peri_set_clk()
[all …]
H A Dclk_rv1126.c633 parent = priv->cpll_hz; in rv1126_pdbus_get_clk()
644 parent = priv->cpll_hz; in rv1126_pdbus_get_clk()
656 parent = priv->cpll_hz; in rv1126_pdbus_get_clk()
679 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rv1126_pdbus_set_clk()
952 parent = priv->cpll_hz; in rv1126_crypto_get_clk()
963 parent = priv->cpll_hz; in rv1126_crypto_get_clk()
974 parent = priv->cpll_hz; in rv1126_crypto_get_clk()
1053 return DIV_TO_RATE(priv->cpll_hz, div) / 2; in rv1126_mmc_get_clk()
1116 parent = priv->cpll_hz; in rv1126_sfc_get_clk()
1148 parent = priv->cpll_hz; in rv1126_nand_get_clk()
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H A Dclk_rk3588.c296 prate = priv->cpll_hz; in rk3588_top_get_clk()
307 prate = priv->cpll_hz; in rk3588_top_get_clk()
336 if (!(priv->cpll_hz % rate)) { in rk3588_top_set_clk()
338 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_top_set_clk()
758 prate = priv->cpll_hz; in rk3588_mmc_get_clk()
770 prate = priv->cpll_hz; in rk3588_mmc_get_clk()
780 prate = priv->cpll_hz; in rk3588_mmc_get_clk()
792 prate = priv->cpll_hz; in rk3588_mmc_get_clk()
824 } else if (!(priv->cpll_hz % rate)) { in rk3588_mmc_set_clk()
826 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_mmc_set_clk()
[all …]
H A Dclk_rk3528.c417 prate = priv->cpll_hz; in rk3528_cgpll_matrix_get_rate()
422 prate = priv->cpll_hz; in rk3528_cgpll_matrix_get_rate()
526 prate = priv->cpll_hz; in rk3528_cgpll_matrix_set_rate()
532 prate = priv->cpll_hz; in rk3528_cgpll_matrix_set_rate()
921 prate = priv->cpll_hz; in rk3528_sdmmc_get_clk()
937 } else if ((priv->cpll_hz % rate) == 0) { in rk3528_sdmmc_set_clk()
938 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3528_sdmmc_set_clk()
968 parent = priv->cpll_hz; in rk3528_sfc_get_clk()
983 } else if ((priv->cpll_hz % rate) == 0) { in rk3528_sfc_set_clk()
984 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3528_sfc_set_clk()
[all …]
H A Dclk_rk3568.c672 return DIV_TO_RATE(priv->cpll_hz, div); in rk3568_cpll_div_get_rate()
726 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3568_cpll_div_set_rate()
1751 parent = priv->cpll_hz; in rk3568_aclk_vop_get_clk()
1765 if ((priv->cpll_hz % rate) == 0) { in rk3568_aclk_vop_set_clk()
1766 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3568_aclk_vop_set_clk()
1811 parent = priv->cpll_hz; in rk3568_dclk_vop_get_clk()
1868 pll_rate = priv->cpll_hz; in rk3568_dclk_vop_set_clk()
2099 p_rate = DIV_TO_RATE(priv->cpll_hz, div); in rk3568_ebc_get_clk()
2120 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3568_ebc_set_clk()
2144 p_rate = priv->cpll_hz; in rk3568_rkvdec_get_clk()
[all …]
H A Dclk_rv1106.c841 p_rate = priv->cpll_hz; in rv1106_uart_get_rate()
869 } else if (priv->cpll_hz % rate == 0) { in rv1106_uart_set_rate()
951 return DIV_TO_RATE(priv->cpll_hz, div); in rv1106_vop_get_clk()
980 if ((priv->cpll_hz % rate) == 0) { in rv1106_vop_set_clk()
982 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rv1106_vop_set_clk()
1280 if (priv->cpll_hz != CPLL_HZ) { in rv1106_clk_init()
1284 priv->cpll_hz = CPLL_HZ; in rv1106_clk_init()
1312 priv->cpll_hz = CPLL_HZ; in rv1106_clk_probe()
H A Dclk_rk322x.c467 parent = priv->cpll_hz; in rk322x_vop_get_clk()
475 parent = priv->cpll_hz; in rk322x_vop_get_clk()
510 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz); in rk322x_vop_set_clk()
651 priv->cpll_hz = rate; in rk322x_clk_set_rate()
963 priv->cpll_hz = rockchip_pll_get_rate(&rk322x_pll_clks[CPLL], in rkclk_init()
998 priv->cpll_hz = CPLL_HZ; in rkclk_init()
H A Dclk_rk1808.c505 parent = priv->cpll_hz; in rk1808_vop_get_clk()
564 if (!(priv->cpll_hz % hz)) { in rk1808_vop_set_clk()
566 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz); in rk1808_vop_set_clk()
1012 priv->cpll_hz = rate; in rk1808_clk_set_rate()
1308 priv->cpll_hz = rockchip_pll_get_rate(&rk1808_pll_clks[CPLL], in rk1808_clk_probe()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk322x.h23 ulong cpll_hz; member
H A Dcru_rk3328.h15 ulong cpll_hz; member
H A Dcru_rv1106.h43 ulong cpll_hz; member
H A Dcru_rk1808.h39 ulong cpll_hz; member
H A Dcru_rv1126.h72 ulong cpll_hz; member
H A Dcru_rk3528.h40 ulong cpll_hz; member
H A Dcru_rk3562.h43 ulong cpll_hz; member
H A Dcru_rv1126b.h40 ulong cpll_hz; member
H A Dcru_rk3588.h46 ulong cpll_hz; member
H A Dcru_rk3568.h51 ulong cpll_hz; member
H A Dcru_rk3576.h46 ulong cpll_hz; member