fix(security): add CVE-2024-7881 mitigation to C1-Ultra CPU

This patch mitigates Cat B erratum 3651221 [2] / CVE-2024-7881 [1]
for C1-Ultra CPU. This CVE applies to r0p0 and is fixed in r1p0 [2].

T

fix(security): add CVE-2024-7881 mitigation to C1-Ultra CPU

This patch mitigates Cat B erratum 3651221 [2] / CVE-2024-7881 [1]
for C1-Ultra CPU. This CVE applies to r0p0 and is fixed in r1p0 [2].

This CVE can be mitigated by disabling the affected prefetcher
setting CPUACTLR6_EL1[41].

[1] https://developer.arm.com/documentation/110326/latest/
[2] https://developer.arm.com/documentation/111077/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I7815d6fc9af812c38b1c05881c850b8209d6ad7c

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fix(security): add CVE-2024-7881 mitigation to C1-Premium CPU

This patch mitigates Cat B erratum 3651221 [2] / CVE-2024-7881 [1]
for C1-Premium CPU. This CVE applies to r0p0 and
is fixed in r1p0 [2]

fix(security): add CVE-2024-7881 mitigation to C1-Premium CPU

This patch mitigates Cat B erratum 3651221 [2] / CVE-2024-7881 [1]
for C1-Premium CPU. This CVE applies to r0p0 and
is fixed in r1p0 [2].

This CVE can be mitigated by disabling the affected prefetcher
setting CPUACTLR6_EL1[41].

[1] https://developer.arm.com/documentation/110326/latest/
[2] https://developer.arm.com/documentation/111078/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I70b50700bc1618e0f8f4121efc9fe89e2742ed74

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Merge changes from topic "xl/a725-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A725 erratum 3456106
fix(cpus): workaround for Cortex-A725 erratum 3711914
fix(cpus): wor

Merge changes from topic "xl/a725-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A725 erratum 3456106
fix(cpus): workaround for Cortex-A725 erratum 3711914
fix(cpus): workaround for Cortex-A725 erratum 2936490
fix(cpus): workaround for Cortex-A725 erratum 2874943

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fix(cpus): workaround for Cortex-A725 erratum 3711914

Cortex-A725 erratum 3711914 is a Cat B erratum that applies
to revisions r0p0 and r0p1 and it is fixed in r0p2.

This erratum can be avoided by

fix(cpus): workaround for Cortex-A725 erratum 3711914

Cortex-A725 erratum 3711914 is a Cat B erratum that applies
to revisions r0p0 and r0p1 and it is fixed in r0p2.

This erratum can be avoided by inserting a DMB LD after each DSB ST instruction.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest/

Change-Id: If3b9d3a0f495b3a172d3e6e5ca7afa8c30aeb4ea
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A725 erratum 2936490

Cortex-A725 erratum 2936490 is a Cat B erratum that applies
to revisions in r0p0, and is fixed in r0p1.

This erratum can be avoided by setting

fix(cpus): workaround for Cortex-A725 erratum 2936490

Cortex-A725 erratum 2936490 is a Cat B erratum that applies
to revisions in r0p0, and is fixed in r0p1.

This erratum can be avoided by setting CPUACTLR2_EL1[37] to 1.
Setting this bit is expected to have a negligible performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest/

Change-Id: I9833f8831ba3735a94763791a65be11b95c00bdb
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A725 erratum 2874943

Cortex-A725 erratum 2874943 is a Cat B erratum that applies
to revision r0p0 when FEAT_SPE is enabled, it is fixed in r0p1.

This erratum can be

fix(cpus): workaround for Cortex-A725 erratum 2874943

Cortex-A725 erratum 2874943 is a Cat B erratum that applies
to revision r0p0 when FEAT_SPE is enabled, it is fixed in r0p1.

This erratum can be avoided by setting bits[58:57] to 0b11 in CPUACTLR_EL1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest/

Change-Id: I686bbde8756d52afee92097ec05b97138b550025
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 1969401

Cortex-A76AE erratum 1969401 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by inserting a

fix(cpus): workaround for Cortex-A76AE erratum 1969401

Cortex-A76AE erratum 1969401 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by inserting a DMB ST before acquire
atomic instructions without release semantics.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: I893452450d430833e6c5a8e33a1e37b708218576
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 1931435

Cortex-A76AE erratum 1931435 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPU

fix(cpus): workaround for Cortex-A76AE erratum 1931435

Cortex-A76AE erratum 1931435 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPUACTLR_EL1[13] to 1. This bit
delays instruction fetch after branch misprediction. This workaround
will have a small impact on performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: I1baba8752f5f2e2ab5c873030e1f00cbb8cf1e60
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 1931427

Cortex-A76AE erratum 1931427 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPU

fix(cpus): workaround for Cortex-A76AE erratum 1931427

Cortex-A76AE erratum 1931427 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPUACTLR2_EL1[2] to 1. The bit
to force Atomic Store operations to write-back memory to be performed
in the L1 data cache.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: I31566838f894372e5627abda8b0bea1505f11f5d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge changes from topic "tc-lsc-25-cpu-libs" into integration

* changes:
feat(cpus): add support for LSC25 E-core CPU
feat(cpus): add support for LSC25 P-core CPU

fix(psci): get the cpu_ops before exiting coherency

It is possible for the cpu_data structure to be cached somewhere in the
cache hierarchy. When HW_ASSISTED_COHERENCY == 0 we flush the core's
priva

fix(psci): get the cpu_ops before exiting coherency

It is possible for the cpu_data structure to be cached somewhere in the
cache hierarchy. When HW_ASSISTED_COHERENCY == 0 we flush the core's
private caches (usually the L1). However, the destination might be
shared caches (eg DSU L2 cache) so when we subsequently dereference the
cpu_data pointer we could get a stale value.

So dereference it prior to disabling the caches to avoid this scenario
and do all accesses from a coherent view of memory.

Change-Id: If118ca8c0436dd04d6ad0d57073d69305a7f41cb
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpus): add support for LSC25 E-core CPU

Add basic CPU library code to support the Large Screen Compute 2025
E-core CPU.

Change-Id: Ibda2e8441d3a3e35941448b483d07e17db2ef234
Signed-off-by: Ryan

feat(cpus): add support for LSC25 E-core CPU

Add basic CPU library code to support the Large Screen Compute 2025
E-core CPU.

Change-Id: Ibda2e8441d3a3e35941448b483d07e17db2ef234
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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feat(cpus): add support for LSC25 P-core CPU

Add basic CPU library code to support the Large Screen Compute 2025
P-core CPU.

Change-Id: Icfd2fdbaed577e64cb2db028416a6eca5ba2cfcf
Signed-off-by: Ryan

feat(cpus): add support for LSC25 P-core CPU

Add basic CPU library code to support the Large Screen Compute 2025
P-core CPU.

Change-Id: Icfd2fdbaed577e64cb2db028416a6eca5ba2cfcf
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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feat(cpus): add support for Neoverse-N2 prefetcher

To get accurate and repeatable L2 cache performance metrics,
the L2 region prefetcher must be disabled. This prevents
speculative fetches from inte

feat(cpus): add support for Neoverse-N2 prefetcher

To get accurate and repeatable L2 cache performance metrics,
the L2 region prefetcher must be disabled. This prevents
speculative fetches from interfering with the measurements.

This patch adds a build-time option, NEOVERSE_N2_PREFETCHER_DISABLE,
to set the PF_DIS bit (bit 15) in the CPUECTLR_EL1 register for this
purpose.

Change-Id: Ie7ab9e84bb29d042d0bb2ec697e0c1e39ad5032e
Signed-off-by: Rohit Ner <rohitner@google.com>

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Merge "feat(cpus): add support for venom cpu" into integration

fix(security): remove CVE_2022_23960 Cortex-X4

Cortex-X4 has ECBHB implemented and is protected against X-Context
attacks.

Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https://d

fix(security): remove CVE_2022_23960 Cortex-X4

Cortex-X4 has ECBHB implemented and is protected against X-Context
attacks.

Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https://developer.arm.com/documentation/102484/0003/The-Cortex-X4--core/Supported-standards-and-specifications?lang=en

Remove WORKAROUND_CVE_2022_23960 for Cortex-X4 to avoid accidental
enabling of this workaround and using loop workaround.

This was accidentally added with
commit@8c87becbc64f2e233ac905aa006d5e15a63a9a8b

Change-Id: I23f5fa748377a920340b3c5a6584ccfadeea901a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(security): remove CVE_2022_23960 Neoverse V3

Neoverse V3 has ECBHB implemented and is protected against X-Context
attacks.

Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https

fix(security): remove CVE_2022_23960 Neoverse V3

Neoverse V3 has ECBHB implemented and is protected against X-Context
attacks.

Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https://developer.arm.com/documentation/107734/0002/The-Neoverse--V3--core/Supported-standards-and-specifications?lang=en

Remove WORKAROUND_CVE_2022_23960 to avoid accidental enabling of this
workaround and using loop workaround.

This was accidentally added with
commit@c2a15217c3053117f4d39233002cb1830fa96670

Change-Id: I13b27c04c3da5ec80fa79422b4ef4fee64738caa
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(security): remove CVE_2022_23960 Cortex-A720

Cortex-A720 has ECBHB implemented and is protected against X-Context
attacks.

Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https

fix(security): remove CVE_2022_23960 Cortex-A720

Cortex-A720 has ECBHB implemented and is protected against X-Context
attacks.

Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https://developer.arm.com/documentation/102530/0002/The-Cortex-A720--core/Supported-standards-and-specifications?lang=en

Remove WORKAROUND_CVE_2022_23960 for Cortex-A720 to avoid accidental
enabling of this workaround and using loop workaround.

This was accidentally added with
commit@c2a15217c3053117f4d39233002cb1830fa96670

Change-Id: I3c68b5f5d85ede37a6a039369de8ed2aa9205395
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(cpus): add support for venom cpu

Add basic CPU library code to support Venom CPU

Change-Id: I84d4cb77b175812811a17e55b4b290585e05d216
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

feat(cpus): add support for Dionysus cpu library

Add basic CPU library code to support the Dionysus CPU.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I4e6b3c7e7369b7cbf0

feat(cpus): add support for Dionysus cpu library

Add basic CPU library code to support the Dionysus CPU.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I4e6b3c7e7369b7cbf0e18d295e5ef5352f621e44

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Merge changes from topic "gr/cpu_lib" into integration

* changes:
feat(cpus): add support for caddo cpu
feat(cpus): add support for veymont cpu

Merge changes from topic "gr/spectre_bhb_updates" into integration

* changes:
fix(security): fix Neoverse V2 CVE-2022-23960
fix(security): fix Cortex-X3 CVE-2022-23960
fix(security): fix Corte

Merge changes from topic "gr/spectre_bhb_updates" into integration

* changes:
fix(security): fix Neoverse V2 CVE-2022-23960
fix(security): fix Cortex-X3 CVE-2022-23960
fix(security): fix Cortex-A715 CVE-2022-23960
fix(security): fix spectre bhb loop count for Cortex-A720

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feat(cpus): add support for caddo cpu

Add basic CPU library code to support Caddo CPU

Change-Id: I4b431771ebe6f23eb02f3301ff656cfcd4956f81
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

feat(cpus): add support for veymont cpu

Add basic CPU library code to support Veymont CPU

Change-Id: I44db5650e7c9cf8fcc368c935574f4702c373dae
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

fix(cpus): workaround for Cortex-A720 erratum 3711910

Cortex-A720 erratum 3711910 is a Cat B erratum that applies to
revisions r0p0, r0p1 and r0p2, and is still open.

SDEN documentation:
https://de

fix(cpus): workaround for Cortex-A720 erratum 3711910

Cortex-A720 erratum 3711910 is a Cat B erratum that applies to
revisions r0p0, r0p1 and r0p2, and is still open.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2439421

Change-Id: Id65d5ba41b96648b07c09df77fb25cc4bdb50800
Signed-off-by: John Powell <john.powell@arm.com>

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