1/* 2 * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue neoverse_v3 26 27.global check_erratum_neoverse_v3_3701767 28 29workaround_reset_start neoverse_v3, ERRATUM(2970647), ERRATA_V3_2970647 30 /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ 31 ldr x0, =0x1 32 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ 33 ldr x0, =0xd5380000 34 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ 35 ldr x0, =0xFFFFFF40 36 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ 37 ldr x0, =0x000080010033f 38 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ 39 isb 40workaround_reset_end neoverse_v3, ERRATUM(2970647) 41 42check_erratum_ls neoverse_v3, ERRATUM(2970647), CPU_REV(0, 0) 43 44workaround_reset_start neoverse_v3, ERRATUM(3696307), ERRATA_V3_3696307 45 sysreg_bit_set NEOVERSE_V3_CPUACTLR6_EL1, BIT(41) 46workaround_reset_end neoverse_v3, ERRATUM(3696307) 47 48check_erratum_ls neoverse_v3, ERRATUM(3696307), CPU_REV(0, 1) 49 50add_erratum_entry neoverse_v3, ERRATUM(3701767), ERRATA_V3_3701767 51 52check_erratum_ls neoverse_v3, ERRATUM(3701767), CPU_REV(0, 2) 53 54workaround_reset_start neoverse_v3, ERRATUM(3734562), ERRATA_V3_3734562 55 mov x0, #2 56 msr NEOVERSE_V3_CPUPSELR_EL3, x0 57 ldr x0, =0xD503225F 58 msr NEOVERSE_V3_CPUPOR_EL3, x0 59 mov x0, 0xFFFFFFFF 60 msr NEOVERSE_V3_CPUPMR_EL3, x0 61 ldr x0, =0x404003FD 62 msr NEOVERSE_V3_CPUPCR_EL3, x0 63workaround_reset_end neoverse_v3, ERRATUM(3734562) 64 65check_erratum_ls neoverse_v3, ERRATUM(3734562), CPU_REV(0, 1) 66 67workaround_reset_start neoverse_v3, ERRATUM(3782181), ERRATA_V3_3782181 68 /* Disable retention control for WFI and WFE. */ 69 mrs x0, NEOVERSE_V3_CPUPWRCTLR_EL1 70 bfi x0, xzr, #NEOVERSE_V3_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT, \ 71 #NEOVERSE_V3_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH 72 bfi x0, xzr, #NEOVERSE_V3_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT, \ 73 #NEOVERSE_V3_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH 74 msr NEOVERSE_V3_CPUPWRCTLR_EL1, x0 75workaround_reset_end neoverse_v3, ERRATUM(3782181) 76 77check_erratum_range neoverse_v3, ERRATUM(3782181), CPU_REV(0, 1), \ 78 CPU_REV(0, 1) 79 80workaround_reset_start neoverse_v3, ERRATUM(3864536), ERRATA_V3_3864536 81 sysreg_bit_set NEOVERSE_V3_CPUACTLR2_EL1, BIT(22) 82workaround_reset_end neoverse_v3, ERRATUM(3864536) 83 84check_erratum_ls neoverse_v3, ERRATUM(3864536), CPU_REV(0, 2) 85 86workaround_reset_start neoverse_v3, ERRATUM(3878291), ERRATA_V3_3878291 87 sysreg_bit_set NEOVERSE_V3_CPUACTLR4_EL1, BIT(57) 88workaround_reset_end neoverse_v3, ERRATUM(3878291) 89 90check_erratum_ls neoverse_v3, ERRATUM(3878291), CPU_REV(0, 2) 91 92/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 93workaround_reset_start neoverse_v3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 94 sysreg_bit_set NEOVERSE_V3_CPUECTLR_EL1, BIT(46) 95workaround_reset_end neoverse_v3, CVE(2024, 5660) 96 97check_erratum_ls neoverse_v3, CVE(2024, 5660), CPU_REV(0, 1) 98 99 /* ---------------------------------------------------------------- 100 * CVE-2024-7881 is mitigated for Neoverse-V3 / Neoverse-V3AE 101 * using erratum 3696307 workaround by disabling the 102 * affected prefetcher setting CPUACTLR6_EL1[41]. 103 * ---------------------------------------------------------------- 104 */ 105workaround_reset_start neoverse_v3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 106 sysreg_bit_set NEOVERSE_V3_CPUACTLR6_EL1, BIT(41) 107workaround_reset_end neoverse_v3, CVE(2024, 7881) 108 109check_erratum_ls neoverse_v3, CVE(2024, 7881), CPU_REV(0, 1) 110 111 /* --------------------------------------------- 112 * HW will do the cache maintenance while powering down 113 * --------------------------------------------- 114 */ 115func neoverse_v3_core_pwr_dwn 116 /* --------------------------------------------- 117 * Enable CPU power down bit in power control register 118 * --------------------------------------------- 119 */ 120 sysreg_bit_set NEOVERSE_V3_CPUPWRCTLR_EL1, \ 121 NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 122 123 isb 124 ret 125endfunc neoverse_v3_core_pwr_dwn 126 127cpu_reset_func_start neoverse_v3 128 /* Disable speculative loads */ 129 msr SSBS, xzr 130cpu_reset_func_end neoverse_v3 131 132 /* --------------------------------------------- 133 * This function provides Neoverse V3 specific 134 * register information for crash reporting. 135 * It needs to return with x6 pointing to 136 * a list of register names in ascii and 137 * x8 - x15 having values of registers to be 138 * reported. 139 * --------------------------------------------- 140 */ 141.section .rodata.neoverse_v3_regs, "aS" 142neoverse_v3_regs: /* The ascii list of register names to be reported */ 143 .asciz "cpuectlr_el1", "" 144 145func neoverse_v3_cpu_reg_dump 146 adr x6, neoverse_v3_regs 147 mrs x8, NEOVERSE_V3_CPUECTLR_EL1 148 ret 149endfunc neoverse_v3_cpu_reg_dump 150 151declare_cpu_ops neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \ 152 neoverse_v3_reset_func, \ 153 neoverse_v3_core_pwr_dwn 154 155declare_cpu_ops neoverse_v3, NEOVERSE_V3_MIDR, \ 156 neoverse_v3_reset_func, \ 157 neoverse_v3_core_pwr_dwn 158