1Arm CPU Specific Build Macros 2============================= 3 4This document describes the various build options present in the CPU specific 5operations framework to enable errata workarounds and to enable optimizations 6for a specific CPU on a platform. 7 8Security Vulnerability Workarounds 9---------------------------------- 10 11TF-A exports a series of build flags which control which security 12vulnerability workarounds should be applied at runtime. 13 14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for 15 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none 16 of the PEs in the system need the workaround. Setting this flag to 0 provides 17 no performance benefit for non-affected platforms, it just helps to comply 18 with the recommendation in the spec regarding workaround discovery. 19 Defaults to 1. 20 21- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for 22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep 23 the default value of 1 even on platforms that are unaffected by 24 CVE-2018-3639, in order to comply with the recommendation in the spec 25 regarding workaround discovery. 26 27- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for 28 `CVE-2018-3639`_. This build option should be set to 1 if the target 29 platform contains at least 1 CPU that requires dynamic mitigation. 30 Defaults to 0. 31 32- ``WORKAROUND_CVE_2022_23960``: Enables mitigation for `CVE-2022-23960`_. 33 This build option should be set to 1 if the target platform contains at 34 least 1 CPU that requires this mitigation. Defaults to 1. 35 36- ``WORKAROUND_CVE_2024_5660``: Enables mitigation for `CVE-2024-5660`. 37 The fix is to disable hardware page aggregation by setting CPUECTLR_EL1[46] 38 in EL3 FW. This build option should be set to 1 if the target platform contains 39 at least 1 CPU that requires this mitigation. Defaults to 1. 40 41- ``WORKAROUND_CVE_2024_7881``: Enables mitigation for `CVE-2024-7881`. 42 This build option should be set to 1 if the target platform contains at 43 least 1 CPU that requires this mitigation. Defaults to 1. 44 45.. _arm_cpu_macros_errata_workarounds: 46 47CPU Errata Workarounds 48---------------------- 49 50TF-A exports a series of build flags which control the errata workarounds that 51are applied to each CPU by the reset handler. The errata details can be found 52in the CPU specific errata documents published by Arm: 53For example: `Cortex-A72 MPCore Software Developers Errata Notice`_ 54 55The errata workarounds are implemented for a particular revision or a set of 56processor revisions. This is checked by the reset handler at runtime. Each 57errata workaround is identified by its ``ID`` as specified in the processor's 58errata notice document. The format of the define used to enable/disable the 59errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` 60is for example ``A57`` for the ``Cortex_A57`` CPU. 61 62Refer to :ref:`firmware_design_cpu_errata_implementation` for information on how to 63write errata workaround functions. 64 65All workarounds are disabled by default. The platform is responsible for 66enabling these workarounds according to its requirement by defining the 67errata workaround build flags in the platform specific makefile. In case 68these workarounds are enabled for the wrong CPU revision then the errata 69workaround is not applied. In the DEBUG build, this is indicated by 70printing a warning to the crash console. 71 72In the current implementation, a platform which has more than 1 variant 73with different revisions of a processor has no runtime mechanism available 74for it to specify which errata workarounds should be enabled or not. 75 76The value of the build flags is 0 by default, that is, disabled. A value of 1 77will enable it. 78 79For Cortex-A9, the following errata build flags are defined : 80 81- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9 82 CPU. This needs to be enabled for all revisions of the CPU. 83 84For Cortex-A15, the following errata build flags are defined : 85 86- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 87 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 88 89- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 90 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 91 92For Cortex-A17, the following errata build flags are defined : 93 94- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17 95 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 96 97- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 98 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 99 100For Cortex-A35, the following errata build flags are defined : 101 102- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 103 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35. 104 105For Cortex-A53, the following errata build flags are defined : 106 107- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all 108 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53. 109 110- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all 111 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 112 113- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 114 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. 115 116- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all 117 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 118 119- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and 120 link time to Cortex-A53 CPU. This needs to be enabled for some variants of 121 revision <= r0p4. This workaround can lead the linker to create ``*.stub`` 122 sections. 123 124- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 125 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From 126 r0p4 and onwards, this errata is enabled by default in hardware. Identical to 127 ``A53_DISABLE_NON_TEMPORAL_HINT``. 128 129- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time 130 to Cortex-A53 CPU. This needs to be enabled for some variants of revision 131 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections 132 which are 4kB aligned. 133 134- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 135 CPUs. Though the erratum is present in every revision of the CPU, 136 this workaround is only applied to CPUs from r0p3 onwards, which feature 137 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. 138 Earlier revisions of the CPU have other errata which require the same 139 workaround in software, so they should be covered anyway. 140 141- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all 142 revisions of Cortex-A53 CPU. 143 144For Cortex-A55, the following errata build flags are defined : 145 146- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 147 CPU. This needs to be enabled only for revision r0p0 of the CPU. 148 149- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 150 CPU. This needs to be enabled only for revision r0p0 of the CPU. 151 152- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 153 CPU. This needs to be enabled only for revision r0p0 of the CPU. 154 155- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 156 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 157 158- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 159 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 160 161- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55 162 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 163 164- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all 165 revisions of Cortex-A55 CPU. 166 167For Cortex-A57, the following errata build flags are defined : 168 169- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 170 CPU. This needs to be enabled only for revision r0p0 of the CPU. 171 172- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 173 CPU. This needs to be enabled only for revision r0p0 of the CPU. 174 175- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 176 CPU. This needs to be enabled only for revision r0p0 of the CPU. 177 178- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 179 CPU. This needs to be enabled only for revision r0p0 of the CPU. 180 181- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 182 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 183 184- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 185 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 186 187- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 188 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 189 190- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 191 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 192 193- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 194 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 195 196- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 197 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 198 199- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 200 CPU. This needs to be enabled only for revision <= r1p3 of the CPU. 201 202- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all 203 revisions of Cortex-A57 CPU. 204 205For Cortex-A65, the following errata build flags are defined : 206 207- ``ERRATA_A65_1179935``: This applies errata 1179935 workaround to Cortex-A65 208 CPU. This needs to be enabled only for revision r0p0 of the CPU, and is fixed 209 in r1p0. 210 211- ``ERRATA_A65_1227419``: This applies errata 1227419 workaround to Cortex-A65 212 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU and 213 is fixed in r1p1. 214 215- ``ERRATA_A65_1541130``: This applies errata 1541130 workaround to r0p0, r1p0, 216 r1p1, r1p2 revisions of the CPU and is still open. 217 218For Cortex-A72, the following errata build flags are defined : 219 220- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 221 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. 222 223- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all 224 revisions of Cortex-A72 CPU. 225 226For Cortex-A73, the following errata build flags are defined : 227 228- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 229 CPU. This needs to be enabled only for revision r0p0 of the CPU. 230 231- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 232 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 233 234For Cortex-A75, the following errata build flags are defined : 235 236- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 237 CPU. This needs to be enabled only for revision r0p0 of the CPU. 238 239- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 240 CPU. This needs to be enabled only for revision r0p0 of the CPU. 241 242For Cortex-A76, the following errata build flags are defined : 243 244- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 245 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 246 247- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 248 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 249 250- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 251 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 252 253- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 254 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 255 256- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 257 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 258 259- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 260 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 261 262- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 263 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 264 265- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 266 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 267 268- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all 269 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to 270 limitation of errata framework this errata is applied to all revisions 271 of Cortex-A76 CPU. 272 273- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76 274 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 275 276- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76 277 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU. 278 279- ``ERRATA_A76_2743102``: This applies errata 2743102 workaround to Cortex-A76 280 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 281 still open. 282 283For Cortex-A76AE, the following errata build flags are defined : 284 285- ``ERRATA_A76AE_1931427``: This applies errata 1931427 workaround to Cortex-A76AE 286 CPU. This needs to be enabled for revision r0p0 and r1p0 of the CPU and it is 287 fixed in r1p1. 288 289- ``ERRATA_A76AE_1931435``: This applies errata 1931435 workaround to Cortex-A76AE 290 CPU. This needs to be enabled for revision r0p0 and r1p0 of the CPU and it is 291 fixed in r1p1. 292 293- ``ERRATA_A76AE_1969401``: This applies errata 1969401 workaround to Cortex-A76AE 294 CPU. This needs to be enabled for revision r0p0 and r1p0 of the CPU and it is 295 fixed in r1p1. 296 297- ``ERRATA_A76AE_2371140``: This applies errata 2371140 workaround to Cortex-A76AE 298 CPU. This needs to be enabled for all revisions <= r1p1 of the CPU and is 299 still open. 300 301For Cortex-A77, the following errata build flags are defined : 302 303- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 304 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 305 306- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77 307 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 308 309- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77 310 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 311 312- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77 313 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 314 315- ``ERRATA_A77_2356587``: This applies errata 2356587 workaround to Cortex-A77 316 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 317 318 - ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77 319 CPU. This needs to be enabled for revisions <= r1p1 of the CPU. 320 321 - ``ERRATA_A77_2743100``: This applies errata 2743100 workaround to Cortex-A77 322 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 323 324For Cortex-A78, the following errata build flags are defined : 325 326- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 327 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU. 328 329- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78 330 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 331 332- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78 333 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same 334 issue but there is no workaround for that revision. 335 336- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78 337 CPU. This needs to be enabled for revisions r0p0 and r1p0. 338 339- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78 340 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0. 341 342- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78 343 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue 344 is present in r0p0 but there is no workaround. It is still open. 345 346- ``ERRATA_A78_2376745``: This applies errata 2376745 workaround to Cortex-A78 347 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 348 it is still open. 349 350- ``ERRATA_A78_2395406``: This applies errata 2395406 workaround to Cortex-A78 351 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 352 it is still open. 353 354- ``ERRATA_A78_2712571``: This applies erratum 2712571 workaround to Cortex-A78 355 CPU, this erratum affects system configurations that do not use an ARM 356 interconnect IP. This needs to be enabled for revisions r0p0, r1p0, r1p1 357 and r1p2 and it is still open. 358 359- ``ERRATA_A78_2742426``: This applies erratum 2742426 workaround to Cortex-A78 360 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 361 it is still open. 362 363- ``ERRATA_A78_2772019``: This applies errata 2772019 workaround to Cortex-A78 364 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 365 it is still open. 366 367- ``ERRATA_A78_2779479``: This applies erratum 2779479 workaround to Cortex-A78 368 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 369 it is still open. 370 371For Cortex-A78AE, the following errata build flags are defined : 372 373- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to 374 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. 375 This erratum is still open. 376 377- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to 378 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 379 erratum is still open. 380 381- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to 382 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 383 This erratum is still open. 384 385- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to 386 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 387 erratum is still open. 388 389- ``ERRATA_A78_AE_2712574`` : This applies erratum 2712574 workaround to 390 Cortex-A78AE CPU. This erratum affects system configurations that do not use 391 an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and 392 r0p2. This erratum is still open. 393 394For Cortex-A78C, the following errata build flags are defined : 395 396- ``ERRATA_A78C_1827430`` : This applies errata 1827430 workaround to 397 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 398 fixed in r0p1. 399 400- ``ERRATA_A78C_1827440`` : This applies errata 1827440 workaround to 401 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 402 fixed in r0p1. 403 404- ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to 405 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 406 it is still open. 407 408- ``ERRATA_A78C_2376749`` : This applies errata 2376749 workaround to 409 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 410 erratum is still open. 411 412- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to 413 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 414 erratum is still open. 415 416- ``ERRATA_A78C_2683027`` : This applies errata 2683027 workaround to 417 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 418 erratum is still open. 419 420- ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to 421 Cortex-A78C CPU, this erratum affects system configurations that do not use 422 an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2 423 and is still open. 424 425- ``ERRATA_A78C_2743232`` : This applies erratum 2743232 workaround to 426 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 427 This erratum is still open. 428 429- ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to 430 Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 431 This erratum is still open. 432 433- ``ERRATA_A78C_2779484`` : This applies errata 2779484 workaround to 434 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 435 This erratum is still open. 436 437For Cortex-X1 CPU, the following errata build flags are defined: 438 439- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1 440 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 441 442- ``ERRATA_X1_1688305`` : This applies errata 1688305 workaround to Cortex-X1 443 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 444 445- ``ERRATA_X1_1827429`` : This applies errata 1827429 workaround to Cortex-X1 446 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 447 448For Neoverse N1, the following errata build flags are defined : 449 450- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 451 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. 452 453- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 454 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 455 456- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 457 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 458 459- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 460 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 461 462- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1 463 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 464 465- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1 466 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 467 468- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1 469 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 470 471- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1 472 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 473 474- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1 475 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 476 477- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 478 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 479 480- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1 481 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU. 482 483- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1 484 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 485 486- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1 487 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for 488 revisions r0p0, r1p0, and r2p0 there is no workaround. 489 490- ``ERRATA_N1_2743102``: This applies errata 2743102 workaround to Neoverse-N1 491 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 492 still open. 493 494For Neoverse V1, the following errata build flags are defined : 495 496- ``ERRATA_V1_1618635``: This applies errata 1618635 workaround to Neoverse-V1 497 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 498 r1p0. 499 500- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1 501 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 502 in r1p1. 503 504- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1 505 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 506 in r1p1. 507 508- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1 509 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 510 in r1p1. 511 512- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1 513 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 514 515- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1 516 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the 517 CPU. 518 519- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1 520 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 521 issue is present in r0p0 as well but there is no workaround for that 522 revision. It is still open. 523 524- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1 525 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the 526 CPU. It is still open. 527 528- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1 529 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 530 issue is present in r0p0 as well but there is no workaround for that 531 revision. It is still open. 532 533- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1 534 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 and r1p2 of 535 the CPU. 536 537- ``ERRATA_V1_2348377``: This applies errata 2348377 workaroud to Neoverse-V1 538 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 539 It has been fixed in r1p2. 540 541- ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1 542 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 543 It is still open. 544 545- ``ERRATA_V1_2701953``: This applies erratum 2701953 workaround to Neoverse-V1 546 CPU, this erratum affects system configurations that do not use an ARM 547 interconnect IP. This needs to be enabled for revisions r0p0, r1p0 and r1p1. 548 It has been fixed in r1p2. 549 550- ``ERRATA_V1_2743093``: This applies errata 2743093 workaround to Neoverse-V1 551 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the 552 CPU. It is still open. 553 554- ``ERRATA_V1_2743233``: This applies erratum 2743233 workaround to Neoverse-V1 555 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2 of the 556 CPU. It is still open. 557 558- ``ERRATA_V1_2779461``: This applies erratum 2779461 workaround to Neoverse-V1 559 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the 560 CPU. It is still open. 561 562For Neoverse V2, the following errata build flags are defined : 563 564- ``ERRATA_V2_2618597``: This applies errata 2618597 workaround to Neoverse-V2 565 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 566 r0p2. 567 568- ``ERRATA_V2_2662553``: This applies errata 2662553 workaround to Neoverse-V2 569 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 570 r0p2. 571 572- ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2 573 CPU, this affects system configurations that do not use and ARM interconnect 574 IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed 575 in r0p2. 576 577- ``ERRATA_V2_2719105``: This applies errata 2719105 workaround to Neoverse-V2 578 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 579 r0p2. 580 581- ``ERRATA_V2_2743011``: This applies errata 2743011 workaround to Neoverse-V2 582 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 583 r0p2. 584 585- ``ERRATA_V2_2779510``: This applies errata 2779510 workaround to Neoverse-V2 586 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 587 r0p2. 588 589- ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2 590 CPU, this affects all configurations. This needs to be enabled for revisions 591 r0p0 and r0p1. It has been fixed in r0p2. 592 593- ``ERRATA_V2_3442699``: This applies errata 3442699 workaround to Neoverse-V2 594 CPU. This needs to be enabled for revision r0p0 - r0p2 and is still open. 595 596- ``ERRATA_V2_3701771``: This applies errata 3701771 workaround to Neoverse-V2 597 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 and is 598 still open. 599 600- ``ERRATA_V2_3841324``: This applies errata 3841324 workaround to Neoverse-V2 601 CPU. This needs to be enabled only for revisions r0p0 and r0p1 of 602 the CPU. It is fixed in r0p2. 603 604For Neoverse V3, the following errata build flags are defined : 605 606- ``ERRATA_V3_2970647``: This applies errata 2970647 workaround to Neoverse-V3 607 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 608 609- ``ERRATA_V3_3701767``: This applies errata 3701767 workaround to Neoverse-V3 610 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 of the CPU and 611 is still open. 612 613For Cortex-A710, the following errata build flags are defined : 614 615- ``ERRATA_A710_1901946``: This applies errata 1901946 workaround to 616 Cortex-A710 CPU. This needs to be enabled only for revision r1p0. It has 617 been fixed in r2p0. 618 619- ``ERRATA_A710_1916945``: This applies errata 1916945 workaround to 620 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 621 It has been fixed in r2p0. 622 623- ``ERRATA_A710_1917258``: This applies errata 1917258 workaround to 624 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 625 It has been fixed in r2p0. 626 627- ``ERRATA_A710_1927200``: This applies errata 1927200 workaround to 628 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 629 It has been fixed in r2p0. 630 631- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to 632 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 633 r2p0 of the CPU. It is still open. 634 635- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to 636 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 637 r2p0 of the CPU. It is still open. 638 639- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to 640 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU 641 and is still open. 642 643- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to 644 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 645 of the CPU and is still open. 646 647- ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to 648 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and 649 is still open. 650 651- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to 652 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 653 of the CPU and is fixed in r2p1. 654 655- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to 656 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 657 of the CPU and is fixed in r2p1. 658 659- ``ERRATA_A710_2147715``: This applies errata 2147715 workaround to 660 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU 661 and is fixed in r2p1. 662 663- ``ERRATA_A710_2216384``: This applies errata 2216384 workaround to 664 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 665 of the CPU and is fixed in r2p1. 666 667- ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to 668 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 669 r2p1 of the CPU and is still open. 670 671- ``ERRATA_A710_2291219``: This applies errata 2291219 workaround to 672 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 673 of the CPU and is fixed in r2p1. 674 675- ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to 676 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 677 of the CPU and is fixed in r2p1. 678 679- ``ERRATA_A710_2371105``: This applies errata 2371105 workaround to 680 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 681 of the CPU and is fixed in r2p1. 682 683- ``ERRATA_A710_2701952``: This applies erratum 2701952 workaround to Cortex-A710 684 CPU, and applies to system configurations that do not use and ARM 685 interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and 686 is still open. 687 688- ``ERRATA_A710_2742423``: This applies errata 2742423 workaround to 689 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 690 r2p1 of the CPU and is still open. 691 692- ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to 693 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 694 r2p1 of the CPU and is still open. 695 696- ``ERRATA_A710_2778471``: This applies errata 2778471 workaround to Cortex-A710 697 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 698 CPU and is still open. 699 700- ``ERRATA_A710_3324338``: This applies errata 3324338 workaround to 701 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 702 r2p1 of the CPU and is still open. 703 704- ``ERRATA_A710_3701772``: This applies errata 3701772 workaround to Cortex-A710 705 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0, r2p1 of the 706 CPU and is still open. 707 708For Neoverse N2, the following errata build flags are defined : 709 710- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 711 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 712 713- ``ERRATA_N2_2009478``: This applies errata 2009478 workaround to Neoverse-N2 714 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 715 716- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 717 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 718 719- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 720 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 721 722- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2 723 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 724 725- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 726 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 727 728- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 729 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 730 731- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2 732 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 733 734- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2 735 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 736 737- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2 738 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 739 740- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2 741 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 742 r0p1. 743 744- ``ERRATA_N2_2340933``: This applies errata 2340933 workaround to Neoverse-N2 745 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 746 r0p1. 747 748- ``ERRATA_N2_2346952``: This applies errata 2346952 workaround to Neoverse-N2 749 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU, 750 it is fixed in r0p3. 751 752- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2 753 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open. 754 755- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2 756 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 757 r0p1. 758 759- ``ERRATA_N2_2743014``: This applies errata 2743014 workaround to Neoverse-N2 760 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 761 in r0p3. 762 763- ``ERRATA_N2_2743089``: This applies errata 2743089 workaround to Neoverse-N2 764 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 765 in r0p3. 766 767- ``ERRATA_N2_2728475``: This applies erratum 2728475 workaround to Neoverse-N2 768 CPU, this erratum affects system configurations that do not use and ARM 769 interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 770 It is fixed in r0p3. 771 772- ``ERRATA_N2_2779511``: This applies errata 2779511 workaround to Neoverse-N2 773 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 774 in r0p3. 775 776- ``ERRATA_N2_3701773``: This applies errata 3701773 workaround to Neoverse-N2 777 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is 778 still open. 779 780For Neoverse N3, the following errata build flags are defined : 781 782- ``ERRATA_N3_3699563``: This applies errata 3699563 workaround to Neoverse-N3 783 CPU. This needs to be enabled for revisions r0p0 and is still open. 784 785For Cortex-X2, the following errata build flags are defined : 786 787- ``ERRATA_X2_1901946``: This applies errata 1901946 workaround to Cortex-X2 788 CPU. This needs to be enabled only for r1p0, it is fixed in r2p0. 789 790- ``ERRATA_X2_1916945``: This applies errata 1916945 workaround to Cortex-X2 791 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 792 is fixed in r2p0. 793 794- ``ERRATA_X2_1917258``: This applies errata 1917258 workaround to Cortex-X2 795 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 796 is fixed in r2p0. 797 798- ``ERRATA_X2_1927200``: This applies errata 1927200 workaround to Cortex-X2 799 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 800 is fixed in r2p0. 801 802- ``ERRATA_X2_1934260``: This applies errata 1934260 workaround to Cortex-X2 803 CPU. This needs to be enabled only for revision r1p0 of the CPU, it is fixed 804 in r2p0. 805 806- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 807 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 808 CPU, it is fixed in r2p1. 809 810- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to Cortex-X2 811 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 812 CPU, it is fixed in r2p1. 813 814- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to Cortex-X2 815 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 816 CPU, it is fixed in r2p1. 817 818- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2 819 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed 820 in r2p1. 821 822- ``ERRATA_X2_2136059``: This applies errata 2136059 workaround to Cortex-X2 823 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 824 CPU, it is fixed in r2p1. 825 826- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to Cortex-X2 827 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed 828 in r2p1. 829 830- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to Cortex-X2 831 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 832 CPU, it is fixed in r2p1. 833 834- ``ERRATA_X2_2267065``: This applies errata 2267065 workaround to Cortex-X2 835 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 836 CPU, it is fixed in r2p1. 837 838- ``ERRATA_X2_2282622``: This applies errata 2282622 workaround to Cortex-X2 839 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 840 CPU and is still open. 841 842- ``ERRATA_X2_2291219``: This applies errata 2291219 workaround to Cortex-X2 843 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 844 CPU, it is fixed in r2p1. 845 846- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to Cortex-X2 847 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 848 CPU, it is fixed in r2p1. 849 850- ``ERRATA_X2_2701952``: This applies errata 2701952 workaround to Cortex-X2 851 CPU and affects system configurations that do not use an Arm interconnect IP. 852 This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is 853 still open. 854 855- ``ERRATA_X2_2742423``: This applies errata 2742423 workaround to Cortex-X2 856 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 857 CPU and is still open. 858 859- ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2 860 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 861 CPU and is still open. 862 863- ``ERRATA_X2_2778471``: This applies errata 2778471 workaround to Cortex-X2 864 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 865 CPU and is still open. 866 867- ``ERRATA_X2_3324338``: This applies errata 3324338 workaround to Cortex-X2 868 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 869 CPU and is still open. 870 871- ``ERRATA_X2_3701772``: This applies errata 3701772 workaround to Cortex-X2 872 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 873 CPU and is still open. 874 875For Cortex-X3, the following errata build flags are defined : 876 877- ``ERRATA_X3_2266875``: This applies errata 2266875 workaround to the Cortex-X3 878 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 879 is fixed in r1p1. 880 881- ``ERRATA_X3_2302506``: This applies errata 2302506 workaround to the Cortex-X3 882 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1, it is 883 fixed in r1p2. 884 885- ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to 886 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 887 of the CPU, it is fixed in r1p1. 888 889- ``ERRATA_X3_2372204``: This applies errata 2372204 workaround to 890 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 891 of the CPU, it is fixed in r1p1. 892 893- ``ERRATA_X3_2615812``: This applies errata 2615812 workaround to Cortex-X3 894 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 895 CPU, it is fixed in r1p2. 896 897- ``ERRATA_X3_2641945``: This applies errata 2641945 workaround to Cortex-X3 898 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU. 899 It is fixed in r1p1. 900 901- ``ERRATA_X3_2701951``: This applies erratum 2701951 workaround to Cortex-X3 902 CPU and affects system configurations that do not use an ARM interconnect 903 IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed 904 in r1p2. 905 906- ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to 907 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 908 r1p1. It is fixed in r1p2. 909 910- ``ERRATA_X3_2743088``: This applies errata 2743088 workaround to Cortex-X3 911 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1. It is 912 fixed in r1p2. 913 914- ``ERRATA_X3_2779509``: This applies errata 2779509 workaround to Cortex-X3 915 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 916 CPU. It is fixed in r1p2. 917 918- ``ERRATA_X3_3213672``: This applies errata 3213672 workaround to Cortex-X3 919 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 920 of the CPU. It is still open. 921 922- ``ERRATA_X3_3692984``: This applies errata 3692984 workaround to Cortex-X3 923 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 924 of the CPU. It is still open. 925 926- ``ERRATA_X3_3701769``: This applies errata 3701769 workaround to Cortex-X3 927 CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 928 of the CPU and it is still open. 929 930- ``ERRATA_X3_3827463``: This applies errata 3827463 workaround to Cortex-X3 931 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of 932 the CPU. It is fixed in r1p2. 933 934For Cortex-X4, the following errata build flags are defined : 935 936- ``ERRATA_X4_2701112``: This applies erratum 2701112 workaround to Cortex-X4 937 CPU and affects system configurations that do not use an Arm interconnect IP. 938 This needs to be enabled for revisions r0p0 and is fixed in r0p1. 939 The workaround for this erratum is not implemented in EL3, but the flag can 940 be enabled/disabled at the platform level. The flag is used when the errata ABI 941 feature is enabled and can assist the Kernel in the process of 942 mitigation of the erratum. 943 944- ``ERRATA_X4_2726228``: This applies erratum 2726228 workaround to Cortex-X4 945 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 946 r0p2. 947 948- ``ERRATA_X4_2740089``: This applies errata 2740089 workaround to Cortex-X4 949 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed 950 in r0p2. 951 952- ``ERRATA_X4_2763018``: This applies errata 2763018 workaround to Cortex-X4 953 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 954 955- ``ERRATA_X4_2816013``: This applies errata 2816013 workaround to Cortex-X4 956 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 957 958- ``ERRATA_X4_2897503``: This applies errata 2897503 workaround to Cortex-X4 959 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 960 961- ``ERRATA_X4_2923985``: This applies errata 2923985 workaround to Cortex-X4 962 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 963 964- ``ERRATA_X4_2957258``: This applies errata 2957258 workaround to Cortex-X4 965 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 966 967- ``ERRATA_X4_3076789``: This applies errata 3076789 workaround to Cortex-X4 968 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 969 970- ``ERRATA_X4_3133195``: This applies errata 3133195 workaround to Cortex-X4 971 CPU. This needs to be enabled for revision r0p2. It is fixed in r0p3. 972 973- ``ERRATA_X4_3701758``: This applies errata 3701758 workaround to Cortex-X4 974 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 and r0p3. 975 It is still open. 976 977- ``ERRATA_X4_3887999``: This applies errata 3887999 workaround to Cortex-X4 978 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2 and r0p3. 979 It is still open. 980 981For Cortex-X925, the following errata build flags are defined : 982 983- ``ERRATA_X925_2963999``: This applies errata 2963999 workaround to Cortex-X925 984 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 985 986- ``ERRATA_X925_3701747``: This applies errata 3701747 workaround to Cortex-X925 987 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is still open. 988 989For Cortex-A510, the following errata build flags are defined : 990 991- ``ERRATA_A510_2008766``: This applies errata 2008766 workaround to 992 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 993 r0p3, r1p0, r1p1, r1p2 and r1p3. It is still open. 994 995- ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to 996 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 997 r0p2, r0p3 and r1p0, it is fixed in r1p1. 998 999- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to 1000 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and 1001 r0p2, it is fixed in r0p3. 1002 1003- ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to 1004 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed 1005 in r0p3. The issue is also present in r0p0 and r0p1 but there is no 1006 workaround for those revisions. 1007 1008- ``ERRATA_A510_2080326``: This applies errata 2080326 workaround to 1009 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is 1010 fixed in r0p3. This issue is also present in r0p0 and r0p1 but there is no 1011 workaround for those revisions. 1012 1013- ``ERRATA_A510_2169012``: This applies errata 2169012 workaround to 1014 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 1015 r0p2, r0p3 and r1p0, it is fixed in r1p1. 1016 1017- ``ERRATA_A510_2218134``: This applies errata 2218134 workaround to 1018 Cortex-A510 CPU. This needs to be enabled only for revision r1p0 and is fixed 1019 in r1p1. 1020 1021- ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to 1022 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1023 r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if 1024 ENABLE_MPMM=1. 1025 1026- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to 1027 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1028 r0p3 and r1p0, it is fixed in r1p1. 1029 1030- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to 1031 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1032 r0p3 and r1p0, it is fixed in r1p1. 1033 1034- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to 1035 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1036 r0p3, r1p0 and r1p1. It is fixed in r1p2. 1037 1038- ``ERRATA_A510_2371937``: This applies errata 2371937 workaround to 1039 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 1040 r0p3, r1p0, r1p1, and is fixed in r1p2. 1041 1042- ``ERRATA_A510_2420992``: This applies errata 2420992 workaround to 1043 Cortex-A510 CPU. This needs to applied for revisions r1p0 and r1p1, and is 1044 fixed in r1p2. 1045 1046- ``ERRATA_A510_2666669``: This applies errata 2666669 workaround to 1047 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 1048 r0p3, r1p0, r1p1. It is fixed in r1p2. 1049 1050- ``ERRATA_A510_2684597``: This applies erratum 2684597 workaround to 1051 Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2, 1052 r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. 1053 1054- ``ERRATA_A510_2971420``: This applies erratum 2971420 workaround to 1055 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1056 r1p0, r1p1, r1p2 and r1p3 and is still open. 1057 1058- ``ERRATA_A510_3672349``: This applies erratum 3672349 workaround to 1059 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1060 r1p0, r1p1, r1p2 and r1p3 and is still open. 1061 1062- ``ERRATA_A510_3704847``: This applies erratum 3704847 workaround to 1063 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1064 r1p0, r1p1, r1p2 and r1p3 and is still open. 1065 1066For Cortex-A520, the following errata build flags are defined : 1067 1068- ``ERRATA_A520_2630792``: This applies errata 2630792 workaround to 1069 Cortex-A520 CPU. This needs to applied for revisions r0p0, r0p1 of the 1070 CPU and is still open. 1071 1072- ``ERRATA_A520_2858100``: This applies errata 2858100 workaround to 1073 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1074 It is still open. 1075 1076- ``ERRATA_A520_2938996``: This applies errata 2938996 workaround to 1077 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1078 It is fixed in r0p2. 1079 1080For Cortex-A715, the following errata build flags are defined : 1081 1082- ``ERRATA_A715_2331818``: This applies errata 2331818 workaround to 1083 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. 1084 It is fixed in r1p1. 1085 1086- ``ERRATA_A715_2344187``: This applies errata 2344187 workaround to 1087 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is 1088 fixed in r1p1. 1089 1090- ``ERRATA_A715_2376701``: This applies errata 2376701 workaround to 1091 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is 1092 fixed in r1p1. 1093 1094- ``ERRATA_A715_2409570``: This applies errata 2409570 workaround to 1095 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1096 It is fixed in r1p1. This errata also applies to r0p0 but that revision has a 1097 different workaround, and since r0p0 is not used in production hardware it is 1098 not implemented. 1099 1100- ``ERRATA_A715_2413290``: This applies errata 2413290 workaround to 1101 Cortex-A715 CPU. This needs to be enabled only for revision r1p0 and 1102 when SPE(Statistical profiling extension)=True. The errata is fixed 1103 in r1p1. 1104 1105- ``ERRATA_A715_2420947``: This applies errata 2420947 workaround to 1106 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1107 It is fixed in r1p1. 1108 1109- ``ERRATA_A715_2429384``: This applies errata 2429384 workaround to 1110 Cortex-A715 CPU. This needs to be enabled for revision r1p0. There is no 1111 workaround for revision r0p0. It is fixed in r1p1. 1112 1113- ``ERRATA_A715_2561034``: This applies errata 2561034 workaround to 1114 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1115 It is fixed in r1p1. 1116 1117- ``ERRATA_A715_2728106``: This applies errata 2728106 workaround to 1118 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0 1119 and r1p1. It is fixed in r1p2. 1120 1121- ``ERRATA_A715_2804830``: This applies errata 2804830 workaround to 1122 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1123 r1p1 and r1p2. It is fixed in r1p3. 1124 1125- ``ERRATA_A715_3456084``: This applies errata 3456084 workaround to 1126 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1127 r1p1, r1p2 and r1p3. It is still open. 1128 1129- ``ERRATA_A715_3699560``: This applies errata 3699560 workaround to 1130 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1131 r1p2 and r1p3. It is still open. 1132 1133- ``ERRATA_A715_3711916``: This applies errata 3711916 workaround to 1134 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1135 r1p1, r1p2 and r1p3. It is still open. 1136 1137For Cortex-A720, the following errata build flags are defined : 1138 1139- ``ERRATA_A720_2729604``: This applies errata 2729604 workaround to 1140 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1141 It is fixed in r0p2. 1142 1143- ``ERRATA_A720_2792132``: This applies errata 2792132 workaround to 1144 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1145 It is fixed in r0p2. 1146 1147- ``ERRATA_A720_2844092``: This applies errata 2844092 workaround to 1148 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1149 It is fixed in r0p2. 1150 1151- ``ERRATA_A720_2926083``: This applies errata 2926083 workaround to 1152 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1153 It is fixed in r0p2. 1154 1155- ``ERRATA_A720_2940794``: This applies errata 2940794 workaround to 1156 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1157 It is fixed in r0p2. 1158 1159- ``ERRATA_A720_3456091``: This applies errata 3456091 workaround to 1160 Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 1161 and r0p2. It is still open. 1162 1163- ``ERRATA_A720_3699561``: This applies errata 3699561 workaround to 1164 Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 1165 and r0p2. It is still open. 1166 1167- ``ERRATA_A720_3711910``: This applies errata 3711910 workaround to 1168 Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 1169 and r0p2. It is still open. 1170 1171For Cortex-A720_AE, the following errata build flags are defined : 1172 1173- ``ERRATA_A720_AE_3456103``: This applies errata 3456103 workaround to 1174 Cortex-A720_AE CPU. This needs to be enabled for revisions r0p0 and r0p1. It 1175 is still open. 1176 1177- ``ERRATA_A720_AE_3699562``: This applies errata 3699562 workaround 1178 to Cortex-A720_AE CPU. This needs to be enabled for revisions r0p0. 1179 It is still open. 1180 1181For Cortex-A725, the following errata build flags are defined : 1182 1183- ``ERRATA_A725_2874943``: This applies errata 2874943 workaround to 1184 Cortex-A725 CPU. This needs to be enabled for revisions r0p0 when 1185 FEAT_SPE is enabled. It is fixed in r0p1. 1186 1187- ``ERRATA_A725_2936490``: This applies errata 2936490 workaround to 1188 Cortex-A725 CPU. This needs to be enabled for revisions r0p0. 1189 It is fixed in r0p1. 1190 1191- ``ERRATA_A725_3456106``: This applies errata 3456106 workaround to 1192 Cortex-A725 CPU. This needs to be enabled for revisions r0p0, r0p1 1193 and r0p2. It is still open. 1194 1195- ``ERRATA_A725_3699564``: This applies errata 3699564 workaround to 1196 Cortex-A725 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1197 It is fixed in r0p2. 1198 1199- ``ERRATA_A725_3711914``: This applies errata 3711914 workaround to 1200 Cortex-A725 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1201 It is fixed in r0p2. 1202 1203For C1-Ultra, the following errata build flags are defined : 1204 1205- ``ERRATA_C1ULTRA_3324333``: This applies erratum 3324333 workaround to 1206 C1-Ultra CPU. This needs to be enabled for revision r0p0 and is fixed 1207 in r1p0. 1208 1209- ``ERRATA_C1ULTRA_3502731``: This applies erratum 3502731 workaround to 1210 C1-Ultra CPU. This needs to be enabled for revision r0p0 and is 1211 fixed in r1p0. 1212 1213- ``ERRATA_C1ULTRA_3651221``: This applies erratum 3651221 workaround to 1214 C1-Ultra CPU. This needs to be enabled for revision r0p0 and is 1215 fixed in r1p0. 1216 1217- ``ERRATA_C1ULTRA_3658374``: This applies erratum 3658374 workaround to 1218 C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and 1219 is still open. 1220 1221- ``ERRATA_C1ULTRA_3684152``: This applies erratum 3684152 workaround to 1222 C1-Ultra CPU. This needs to be enabled for revision r0p0 and is 1223 fixed in r1p0. 1224 1225- ``ERRATA_C1ULTRA_3705939``: This applies erratum 3705939 workaround to 1226 C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and 1227 is still open. 1228 1229- ``ERRATA_C1ULTRA_3815514``: This applies erratum 3815514 workaround to 1230 C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and 1231 is still open. 1232 1233- ``ERRATA_C1ULTRA_3865171``: This applies erratum 3865171 workaround to 1234 C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and 1235 is still open. 1236 1237- ``ERRATA_C1ULTRA_3926381``: This applies erratum 3926381 workaround to 1238 C1-Ultra CPU. This needs to be enabled for revision r1p0 and is still 1239 open. 1240 1241- ``ERRATA_C1ULTRA_4102704``: This applies erratum 4102704 workaround to 1242 C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and 1243 is still open. 1244 1245For C1-Premium, the following errata build flags are defined : 1246 1247- ``ERRATA_C1PREMIUM_3324333``: This applies errata 3324333 workaround to 1248 C1-Premium CPU. This needs to be enabled for revision r0p0, and is 1249 fixed in r1p0. 1250 1251- ``ERRATA_C1PREMIUM_3502731``: This applies errata 3502731 workaround to 1252 C1-Premium CPU. This needs to be enabled for revision r0p0, and is fixed 1253 in r1p0. 1254 1255- ``ERRATA_C1PREMIUM_3651221``: This applies errata 3651221 workaround to 1256 C1-Premium CPU. This needs to be enabled for revision r0p0, and is fixed 1257 in r1p0. 1258 1259- ``ERRATA_C1PREMIUM_3684152``: This applies errata 3684152 workaround to 1260 C1-Premium CPU. This needs to be enabled for revision r0p0, and is fixed 1261 in r1p0. 1262 1263- ``ERRATA_C1PREMIUM_3705939``: This applies errata 3705939 workaround to 1264 C1-Premium CPU. This needs to be enabled for revisions r0p0, r1p0 and 1265 is still open. 1266 1267- ``ERRATA_C1PREMIUM_3815514``: This applies errata 3815514 workaround to 1268 C1-Premium CPU. This needs to be enabled for revisions r0p0, r1p0 and 1269 is still open. 1270 1271- ``ERRATA_C1PREMIUM_3865171``: This applies errata 3865171 workaround to 1272 C1-Premium CPU. This needs to be enabled for revisions r0p0, r1p0 and 1273 is still open. 1274 1275- ``ERRATA_C1PREMIUM_3926381``: This applies errata 3926381 workaround to 1276 C1-Premium CPU. This needs to be enabled for revision r1p0 and is 1277 still open. 1278 1279- ``ERRATA_C1PREMIUM_4102704``: This applies errata 4102704 workaround to 1280 C1-Premium CPU. This needs to be enabled for revisions r0p0, r1p0 and 1281 is still open. 1282 1283For C1-Pro, the following errata build flags are defined : 1284 1285- ``ERRATA_C1PRO_3619847``: This applies errata 3619847 workaround to C1-Pro 1286 CPU. This needs to be enabled only for revision r0p0 and is fixed in r1p0. 1287 1288- ``ERRATA_C1PRO_3338470``: This applies errata 3338470 workaround to C1-Pro 1289 CPU. This needs to be enabled only for revision r0p0 and is fixed in r1p0. 1290 1291- ``ERRATA_C1PRO_3362007``: This applies errata 3362007 workaround to C1-Pro 1292 CPU. This needs to be enabled only for revision r0p0 and is fixed in r1p0. 1293 1294- ``ERRATA_C1PRO_3684268``: This applies errata 3684268 workaround to C1-Pro 1295 CPU. This needs to be enabled for revisions r0p0, r1p0 and is fixed in 1296 r1p1. 1297 1298- ``ERRATA_C1PRO_3686597``: This applies errata 3686597 workaround to C1-Pro 1299 CPU. This needs to be enabled for revisions r0p0 and r1p0 of the CPU, it 1300 is fixed in r1p1. 1301 1302- ``ERRATA_C1PRO_3694158``: This applies errata 3694158 workaround to C1-Pro 1303 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 and is 1304 fixed in r1p2. 1305 1306- ``ERRATA_C1PRO_3706576``: This applies errata 3706576 workaround to C1-Pro 1307 CPU. This needs to be enabled for revisions r0p0 and r1p0 of the CPU, it 1308 is fixed in r1p1. 1309 1310- ``ERRATA_C1PRO_3300099``: This applies errata 3300099 workaround to C1-Pro 1311 CPU. This needs to be enabled for revisions r0p0 and r1p0 of the CPU, it 1312 is fixed in r1p1. 1313 1314DSU Errata Workarounds 1315---------------------- 1316 1317Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ 1318Shared Unit) errata. The DSU errata details can be found in the respective Arm 1319documentation: 1320 1321- `Arm DSU Software Developers Errata Notice`_. 1322 1323Each erratum is identified by an ``ID``, as defined in the DSU errata notice 1324document. Thus, the build flags which enable/disable the errata workarounds 1325have the format ``ERRATA_DSU_<ID>``. The implementation and application logic 1326of DSU errata workarounds are similar to `CPU errata workarounds`_. 1327 1328For DSU errata, the following build flags are defined: 1329 1330- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the 1331 affected DSU configurations. This errata applies only for those DSUs that 1332 revision is r0p0 (on r0p1 it is fixed). However, please note that this 1333 workaround results in increased DSU power consumption on idle. 1334 1335- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the 1336 affected DSU configurations. This errata applies only for those DSUs that 1337 contain the ACP interface **and** the DSU revision is older than r2p0 (on 1338 r2p0 it is fixed). However, please note that this workaround results in 1339 increased DSU power consumption on idle. 1340 1341- ``ERRATA_DSU_2313941``: This applies errata 2313941 workaround for the 1342 affected DSU configurations. This errata applies for those DSUs with 1343 revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. However, 1344 please note that this workaround results in increased DSU power consumption 1345 on idle. 1346 1347- ``ERRATA_DSU_2900952``: This applies errata 2900952 workaround for the 1348 affected DSU-120 configurations. This erratum applies to some r2p0 1349 implementations and is fixed in r2p1. The affected r2p0 implementations 1350 are determined by reading the IMP_CLUSTERREVIDR_EL1[1] register bit 1351 and making sure it's clear. 1352 1353CPU Specific optimizations 1354-------------------------- 1355 1356This section describes some of the optimizations allowed by the CPU micro 1357architecture that can be enabled by the platform as desired. 1358 1359- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the 1360 Cortex-A57 cluster power down sequence by not flushing the Level 1 data 1361 cache. The L1 data cache and the L2 unified cache are inclusive. A flush 1362 of the L2 by set/way flushes any dirty lines from the L1 as well. This 1363 is a known safe deviation from the Cortex-A57 TRM defined power down 1364 sequence. Each Cortex-A57 based platform must make its own decision on 1365 whether to use the optimization. 1366 1367- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal 1368 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave 1369 in a way most programmers expect, and will most probably result in a 1370 significant speed degradation to any code that employs them. The Armv8-A 1371 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore 1372 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this 1373 flag enforces this behaviour. This needs to be enabled only for revisions 1374 <= r0p3 of the CPU and is enabled by default. 1375 1376- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as 1377 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be 1378 enabled only for revisions <= r1p2 of the CPU and is enabled by default, 1379 as recommended in section "4.7 Non-Temporal Loads/Stores" of the 1380 `Cortex-A57 Software Optimization Guide`_. 1381 1382- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable 1383 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set 1384 this bit only if their memory system meets the requirement that cache 1385 line fill requests from the Cortex-A57 processor are atomic. Each 1386 Cortex-A57 based platform must make its own decision on whether to use 1387 the optimization. This flag is disabled by default. 1388 1389- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last 1390 level cache(LLC) is present in the system, and that the DataSource field 1391 on the master CHI interface indicates when data is returned from the LLC. 1392 This is used to control how the LL_CACHE* PMU events count. 1393 Default value is 0 (Disabled). 1394 1395- ``NEOVERSE_N2_PREFETCHER_DISABLE``: This flag disables the region prefetcher 1396 on the Neoverse N2 core. This is used during performance analysis to get clean 1397 and repeatable measurements of the cache by preventing speculative data fetches 1398 from interfering with benchmark results. 1399 Default value is 0 (Disabled). 1400 1401GIC Errata Workarounds 1402---------------------- 1403- ``GIC600_ERRATA_WA_2384374``: This flag applies part 2 of errata 2384374 1404 workaround for the affected GIC600 and GIC600-AE implementations. It applies 1405 to implementations of GIC600 and GIC600-AE with revisions less than or equal 1406 to r1p6 and r0p2 respectively. If the platform sets GICV3_SUPPORT_GIC600, 1407 then this flag is enabled; otherwise, it is 0 (Disabled). 1408 1409-------------- 1410 1411*Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.* 1412 1413.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 1414.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 1415.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960 1416.. _CVE-2024-5660: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2024-5660 1417.. _CVE-2024-7881: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2024-7881 1418.. _Cortex-A72 MPCore Software Developers Errata Notice: https://developer.arm.com/documentation/epm012079/latest 1419.. _Cortex-A57 Software Optimization Guide: https://developer.arm.com/documentation/uan0015 1420.. _Arm DSU Software Developers Errata Notice: https://developer.arm.com/documentation/SDEN854652 1421