1 /* 2 * Copyright (c) 2020-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <cortex_a520.h> 11 #include <lib/utils_def.h> 12 #include <lib/xlat_tables/xlat_tables_defs.h> 13 #include <plat/arm/board/common/board_css_def.h> 14 #include <plat/arm/board/common/v2m_def.h> 15 16 /* 17 * arm_def.h depends on the platform system counter macros, so must define the 18 * platform macros before including arm_def.h. 19 */ 20 #if TARGET_PLATFORM == 4 21 #ifdef ARM_SYS_CNTCTL_BASE 22 #error "error: ARM_SYS_CNTCTL_BASE is defined prior to the PLAT_ARM_SYS_CNTCTL_BASE definition" 23 #endif 24 #define PLAT_ARM_SYS_CNTCTL_BASE UL(0x47000000) 25 #define PLAT_ARM_SYS_CNTREAD_BASE UL(0x47010000) 26 #endif 27 28 #include <plat/arm/common/arm_def.h> 29 30 #include <plat/arm/common/arm_spm_def.h> 31 #include <plat/arm/css/common/css_def.h> 32 #include <plat/arm/soc/common/soc_css_def.h> 33 #include <plat/common/common_def.h> 34 35 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ 36 37 #if TRANSFER_LIST 38 /* 39 * Summation of data size of all Transfer Entries included in the Transfer list. 40 * Note: Update this field whenever new Transfer Entries are added in future. 41 */ 42 #define PLAT_ARM_FW_HANDOFF_SIZE U(0x9000) 43 #define PLAT_ARM_EL3_FW_HANDOFF_BASE ARM_BL_RAM_BASE 44 #define PLAT_ARM_EL3_FW_HANDOFF_LIMIT PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE 45 #define FW_NS_HANDOFF_BASE (PLAT_ARM_NS_IMAGE_BASE - PLAT_ARM_FW_HANDOFF_SIZE) 46 47 /* Mappings for Secure and Non-secure Transfer_list */ 48 #define TC_MAP_EL3_FW_HANDOFF MAP_REGION_FLAT( \ 49 PLAT_ARM_EL3_FW_HANDOFF_BASE, \ 50 PLAT_ARM_FW_HANDOFF_SIZE, \ 51 MT_MEMORY | MT_RW | EL3_PAS) 52 53 #define TC_MAP_FW_NS_HANDOFF MAP_REGION_FLAT( \ 54 FW_NS_HANDOFF_BASE, \ 55 PLAT_ARM_FW_HANDOFF_SIZE, \ 56 MT_MEMORY | MT_RW | MT_NS) 57 #endif /* TRANSFER_LIST */ 58 59 /* 60 * The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC, 61 * its base is ARM_AP_TZC_DRAM1_BASE. 62 * 63 * Reserve 96 MB below ARM_AP_TZC_DRAM1_BASE for: 64 * - BL32_BASE when SPD_spmd is enabled 65 * - Region to load secure partitions 66 * 67 * 68 * 0x8000_0000 ------------------ TC_NS_DRAM1_BASE 69 * | DTB | 70 * | (32K) | 71 * 0x8000_8000 ------------------ 72 * | NT_FW_CONFIG | 73 * | (4KB) | 74 * 0x8000_9000 ------------------ 75 * | ... | 76 * 0xf8e0_0000 ------------------ TC_NS_OPTEE_BASE 77 * | OP-TEE shmem | 78 * | (2MB) | 79 * 0xF900_0000 ------------------ TC_TZC_DRAM1_BASE 80 * | | 81 * | SPMC | 82 * | SP | 83 * | (96MB) | 84 * 0xFF00_0000 ------------------ ARM_AP_TZC_DRAM1_BASE 85 * | AP | 86 * | EL3 Monitor | 87 * | SCP | 88 * | (16MB) | 89 * 0xFFFF_FFFF ------------------ 90 * 91 * 92 */ 93 #define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \ 94 TC_TZC_DRAM1_SIZE) 95 #define TC_TZC_DRAM1_SIZE (96 * SZ_1M) /* 96 MB */ 96 #define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \ 97 TC_TZC_DRAM1_SIZE - 1) 98 99 #define TC_NS_DRAM1_BASE ARM_DRAM1_BASE 100 #define TC_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 101 ARM_TZC_DRAM1_SIZE - \ 102 TC_TZC_DRAM1_SIZE) 103 #define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - 1) 104 105 #define TC_NS_OPTEE_SIZE (2 * SZ_1M) 106 #define TC_NS_OPTEE_BASE (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - TC_NS_OPTEE_SIZE) 107 108 /* 109 * Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure) 110 */ 111 #define TC_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 112 TC_NS_DRAM1_BASE, \ 113 TC_NS_DRAM1_SIZE, \ 114 MT_MEMORY | MT_RW | MT_NS) 115 116 117 #define TC_MAP_TZC_DRAM1 MAP_REGION_FLAT( \ 118 TC_TZC_DRAM1_BASE, \ 119 TC_TZC_DRAM1_SIZE, \ 120 MT_MEMORY | MT_RW | MT_SECURE) 121 122 #define PLAT_HW_CONFIG_DTB_BASE TC_NS_DRAM1_BASE 123 #define PLAT_ARM_HW_CONFIG_SIZE ULL(0x8000) 124 125 #define PLAT_DTB_DRAM_NS MAP_REGION_FLAT( \ 126 PLAT_HW_CONFIG_DTB_BASE, \ 127 PLAT_ARM_HW_CONFIG_SIZE, \ 128 MT_MEMORY | MT_RO | MT_NS) 129 /* 130 * Max size of SPMC is 2MB for tc. With SPMD enabled this value corresponds to 131 * max size of BL32 image. 132 */ 133 #if defined(SPD_spmd) 134 #define TC_EL2SPMC_LOAD_ADDR (TC_TZC_DRAM1_BASE + 0x04000000) 135 136 #define PLAT_ARM_SPMC_BASE TC_EL2SPMC_LOAD_ADDR 137 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 138 #endif 139 140 /* 141 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 142 * plat_arm_mmap array defined for each BL stage. 143 */ 144 #if defined(IMAGE_BL31) 145 # if SPM_MM 146 # define PLAT_ARM_MMAP_ENTRIES 9 147 # define MAX_XLAT_TABLES 7 148 # define PLAT_SP_IMAGE_MMAP_REGIONS 7 149 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 150 # else 151 # define PLAT_ARM_MMAP_ENTRIES 8 152 # define MAX_XLAT_TABLES 8 153 # endif 154 #elif defined(IMAGE_BL32) 155 # define PLAT_ARM_MMAP_ENTRIES 8 156 # define MAX_XLAT_TABLES 5 157 #elif !USE_ROMLIB 158 # define PLAT_ARM_MMAP_ENTRIES 11 159 # define MAX_XLAT_TABLES 7 160 #else 161 # define PLAT_ARM_MMAP_ENTRIES 12 162 # define MAX_XLAT_TABLES 6 163 #endif 164 165 /* 166 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 167 * plus a little space for growth. 168 */ 169 #define PLAT_ARM_MAX_BL1_RW_SIZE 0x12000 170 171 /* 172 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 173 */ 174 175 #if USE_ROMLIB 176 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 177 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 178 #else 179 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 180 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 181 #endif 182 183 /* 184 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 185 * little space for growth. Current size is considering that TRUSTED_BOARD_BOOT 186 * and MEASURED_BOOT is enabled. 187 */ 188 # define PLAT_ARM_MAX_BL2_SIZE 0x29000 189 190 191 /* 192 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 193 * calculated using the current BL31 PROGBITS debug size plus the sizes of 194 * BL2 and BL1-RW. Current size is considering that TRUSTED_BOARD_BOOT and 195 * MEASURED_BOOT is enabled. 196 */ 197 #define PLAT_ARM_MAX_BL31_SIZE 0x60000 198 199 /* 200 * Size of cacheable stacks 201 */ 202 #if defined(IMAGE_BL1) 203 # define PLATFORM_STACK_SIZE 0x1000 204 #elif defined(IMAGE_BL2) 205 # define PLATFORM_STACK_SIZE 0x1000 206 #elif defined(IMAGE_BL2U) 207 # define PLATFORM_STACK_SIZE 0x400 208 #elif defined(IMAGE_BL31) 209 # if SPM_MM 210 # define PLATFORM_STACK_SIZE 0x500 211 # else 212 # define PLATFORM_STACK_SIZE 0xb00 213 # endif 214 #elif defined(IMAGE_BL32) 215 # define PLATFORM_STACK_SIZE 0x440 216 #endif 217 218 /* 219 * In the current implementation the RoT Service request that requires the 220 * biggest message buffer is the RSE_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The 221 * maximum required buffer size is calculated based on the platform-specific 222 * needs of this request. 223 */ 224 #define PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE 0x500 225 226 #define TC_DEVICE_BASE 0x21000000 227 #define TC_DEVICE_SIZE 0x5f000000 228 229 #if defined(TARGET_FLAVOUR_FPGA) 230 #undef V2M_FLASH0_BASE 231 #undef V2M_FLASH0_SIZE 232 #if TC_FPGA_FIP_IMG_IN_RAM 233 /* 234 * Note that this is just used for the FIP, which is not required 235 * anymore once Linux has commenced booting. So we are safe allowing 236 * Linux to also make use of this memory and it doesn't need to be 237 * carved out of the devicetree. 238 * 239 * This only needs to match the RAM load address that we give the FIP 240 * on either the FPGA or FVP command line so there is no need to link 241 * it to say halfway through the RAM or anything like that. 242 */ 243 #define V2M_FLASH0_BASE UL(0xB0000000) 244 #else 245 #define V2M_FLASH0_BASE UL(0x0C000000) 246 #endif 247 #define V2M_FLASH0_SIZE UL(0x02000000) 248 #endif 249 250 // TC_MAP_DEVICE covers different peripherals 251 // available to the platform 252 #define TC_MAP_DEVICE MAP_REGION_FLAT( \ 253 TC_DEVICE_BASE, \ 254 TC_DEVICE_SIZE, \ 255 MT_DEVICE | MT_RW | MT_SECURE) 256 257 258 #define TC_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 259 V2M_FLASH0_SIZE, \ 260 MT_DEVICE | MT_RO | MT_SECURE) 261 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 262 263 #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 264 265 /* PLAT_ARM_TRUSTED_ROM_SIZE 512KB minus ROM base. */ 266 #define PLAT_ARM_TRUSTED_ROM_SIZE (0x00080000 - PLAT_ARM_TRUSTED_ROM_BASE) 267 268 #define PLAT_ARM_NSRAM_BASE 0x06000000 269 #if TARGET_FLAVOUR_FVP 270 #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ 271 #else /* TARGET_FLAVOUR_FPGA */ 272 #define PLAT_ARM_NSRAM_SIZE 0x00008000 /* 64KB */ 273 #endif /* TARGET_FLAVOUR_FPGA */ 274 275 /* 276 * Memory Layout "Android Loaded into MMC Card" with MTE carveout 277 * 278 * 0x8_8000_0000 ------------------ PLAT_ARM_DRAM2_BASE 279 * | | 280 * | TC_NS_DRAM2 | 281 * | (13.5GB) | 282 * | | 283 * | | 284 * | | 285 * | | 286 * 0xB_E000_0000 ------------------ PLAT_ARM_DRAM2_END 287 * | MTE | 288 * | TAGS SPACE | 289 * | (512MB) | 290 * 0xC_0000_0000 ------------------ 291 * 292 * ******************************************************** 293 * 294 * Memory Layout "Android Loaded into MMC Card" without MTE carveout 295 * 296 * 0x8_8000_0000 ------------------ PLAT_ARM_DRAM2_BASE 297 * | | 298 * | TC_NS_DRAM2 | 299 * | (14GB) | 300 * | | 301 * | | 302 * | | 303 * | | 304 * 0xC_0000_0000 ------------------ PLAT_ARM_DRAM2_END 305 * 306 * ******************************************************** 307 * 308 * Memory Layout "Android In RAM" with MTE carveout 309 * 310 * 0x8_8000_0000 ------------------ ANDROID_FS_BASE 311 * | | 312 * | | 313 * | ANDROID_IMG | 314 * | (8.5GB) | 315 * | | 316 * | | 317 * 0xA_A000_0000 ------------------ PLAT_ARM_DRAM2_BASE 318 * | | 319 * | TC_NS_DRAM2 | 320 * | (5GB) | 321 * | | 322 * 0xB_E000_0000 ------------------ PLAT_ARM_DRAM2_END 323 * | MTE | 324 * | TAGS SPACE | 325 * | (512MB) | 326 * 0xC_0000_0000 ------------------ 327 */ 328 329 #define TC_DRAM2_BASE ULL(0x880000000) 330 #define TC_TOTAL_DRAM2_SIZE ULL(0x380000000) 331 332 #if TC_FPGA_FS_IMG_IN_RAM 333 /* 8.5GB reserved for system+userdata+vendor images */ 334 #define SYSTEM_IMAGE_SIZE ULL(0xC0000000) /* 3GB */ 335 #define USERDATA_IMAGE_SIZE ULL(0x140000000) /* 5GB */ 336 #define VENDOR_IMAGE_SIZE ULL(0x20000000) /* 512MB */ 337 #define ANDROID_FS_SIZE (SYSTEM_IMAGE_SIZE + \ 338 USERDATA_IMAGE_SIZE + \ 339 VENDOR_IMAGE_SIZE) 340 #else 341 #define ANDROID_FS_SIZE ULL(0) 342 #endif /* TC_FPGA_FS_IMG_IN_RAM */ 343 344 #if defined(TARGET_FLAVOUR_FPGA) && (TARGET_PLATFORM == 4) 345 /* To make optimal use of memory, set this to the address equivalent to the top 346 * 3.125% of the available downstream size. 347 * Note that this assumes total memory of 16GiB split across 8 MCN nodes. 348 */ 349 #define TC_MTU_TAG_ADDR_BASE ULL(0x7C000000) 350 351 /* Calculate total amount of RAM given over to MTE carveout based on the carveout 352 * address 353 */ 354 #define TC_TOTAL_DRAM_AVAILABLE (TC_TOTAL_DRAM2_SIZE + ARM_DRAM1_SIZE) 355 #define TC_DRAM_SIZE_PER_MCN_INST ((TC_TOTAL_DRAM_AVAILABLE) / (MCN_INSTANCES)) 356 #define TC_MTE_SIZE_PER_MCN_INST (TC_DRAM_SIZE_PER_MCN_INST - TC_MTU_TAG_ADDR_BASE) 357 #define TC_MTE_SIZE_TOTAL ((TC_MTE_SIZE_PER_MCN_INST) * (MCN_INSTANCES)) 358 #else 359 #define TC_MTE_SIZE_TOTAL ULL(0) 360 #endif /* defined(TARGET_FLAVOUR_FPGA) && (TARGET_PLATFORM == 4) */ 361 362 #define PLAT_ARM_DRAM2_BASE ((TC_DRAM2_BASE) + (ANDROID_FS_SIZE)) 363 #define PLAT_ARM_DRAM2_SIZE \ 364 ((TC_TOTAL_DRAM2_SIZE) - (ANDROID_FS_SIZE) - (TC_MTE_SIZE_TOTAL)) 365 366 #define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE) 367 368 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_INT_PROPS(grp) 369 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp), \ 370 INTR_PROP_DESC(SBSA_SECURE_WDOG_INTID, \ 371 GIC_HIGHEST_SEC_PRIORITY, grp, \ 372 GIC_INTR_CFG_LEVEL) 373 374 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SPM_BUF_BASE + \ 375 PLAT_SPM_BUF_SIZE) 376 377 #define PLAT_ARM_SP_MAX_SIZE U(0x2000000) 378 379 /******************************************************************************* 380 * Memprotect definitions 381 ******************************************************************************/ 382 /* PSCI memory protect definitions: 383 * This variable is stored in a non-secure flash because some ARM reference 384 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 385 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 386 */ 387 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 388 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 389 390 /* Secure Watchdog Constants */ 391 #define SBSA_SECURE_WDOG_CONTROL_BASE UL(0x2A480000) 392 #define SBSA_SECURE_WDOG_REFRESH_BASE UL(0x2A490000) 393 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 394 #define SBSA_SECURE_WDOG_INTID 86 395 396 #define PLAT_ARM_SCMI_CHANNEL_COUNT 1 397 398 /* Index of SDS region used in the communication with SCP */ 399 #define SDS_SCP_AP_REGION_ID U(0) 400 /* Index of SDS region used in the communication with RSE */ 401 #define SDS_RSE_AP_REGION_ID U(1) 402 /* 403 * Memory region for RSE's shared data storage (SDS) 404 * It is placed right after the SCMI payload area. 405 */ 406 #define PLAT_ARM_RSE_AP_SDS_MEM_BASE (CSS_SCMI_PAYLOAD_BASE + \ 407 CSS_SCMI_PAYLOAD_SIZE_MAX) 408 409 #define PLAT_ARM_CLUSTER_COUNT U(1) 410 #define PLAT_MAX_CPUS_PER_CLUSTER U(8) 411 #define PLAT_MAX_PE_PER_CPU U(1) 412 413 #define PLATFORM_CORE_COUNT (PLAT_MAX_CPUS_PER_CLUSTER * PLAT_ARM_CLUSTER_COUNT) 414 415 /* Message Handling Unit (MHU) base addresses */ 416 #define PLAT_CSS_MHU_BASE UL(0x46000000) 417 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 418 419 /* AP<->RSS MHUs */ 420 #if TARGET_PLATFORM == 3 421 #define PLAT_RSE_AP_SND_MHU_BASE UL(0x49000000) 422 #define PLAT_RSE_AP_RCV_MHU_BASE UL(0x49100000) 423 #elif TARGET_PLATFORM == 4 424 #define PLAT_RSE_AP_SND_MHU_BASE UL(0x49000000) 425 #define PLAT_RSE_AP_RCV_MHU_BASE UL(0x49010000) 426 #endif 427 428 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 429 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 430 431 /* 432 * Physical and virtual address space limits for MMU in AARCH64 433 */ 434 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 435 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 436 437 /* GIC related constants */ 438 #define PLAT_ARM_GICD_BASE UL(0x30000000) 439 #define PLAT_ARM_GICC_BASE UL(0x2C000000) 440 #define PLAT_ARM_GICR_BASE UL(0x30080000) 441 442 /* 443 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 444 * SCP_BL2 size plus a little space for growth. 445 */ 446 #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x30000 447 448 /* 449 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 450 * SCP_BL2U size plus a little space for growth. 451 */ 452 #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x30000 453 454 /* virtual address used by dynamic mem_protect for chunk_base */ 455 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 456 457 #if ARM_GPT_SUPPORT 458 /* 459 * This overrides the default PLAT_ARM_FIP_OFFSET_IN_GPT in board_css_def.h. 460 * Offset of the FIP in the GPT image. BL1 component uses this option 461 * as it does not load the partition table to get the FIP base 462 * address. At sector 48 for TC to align with ATU page size boundaries (8KiB) 463 * (i.e. after reserved sectors 0-47). 464 * Offset = 48 * 512 = 0x6000 465 */ 466 #undef PLAT_ARM_FIP_OFFSET_IN_GPT 467 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x6000 468 #endif /* ARM_GPT_SUPPORT */ 469 470 /* UART related constants */ 471 472 #define TC_UART0 0x2a400000 473 #define TC_UART1 0x2a410000 474 475 /* 476 * TODO: if any more undefs are needed, it's better to consider dropping the 477 * board_css_def.h include above 478 */ 479 #undef PLAT_ARM_BOOT_UART_BASE 480 #undef PLAT_ARM_RUN_UART_BASE 481 482 #undef PLAT_ARM_CRASH_UART_BASE 483 #undef PLAT_ARM_BOOT_UART_CLK_IN_HZ 484 #undef PLAT_ARM_RUN_UART_CLK_IN_HZ 485 486 #undef ARM_CONSOLE_BAUDRATE 487 #define ARM_CONSOLE_BAUDRATE 38400 488 489 #if TARGET_PLATFORM == 3 490 #define TC_UARTCLK 3750000 491 #elif TARGET_PLATFORM == 4 492 #define TC_UARTCLK 4000000 493 #endif /* TARGET_PLATFORM == 3 */ 494 495 496 #if TARGET_FLAVOUR_FVP 497 #define PLAT_ARM_BOOT_UART_BASE TC_UART1 498 #else /* TARGET_FLAVOUR_FPGA */ 499 #define PLAT_ARM_BOOT_UART_BASE TC_UART0 500 #endif /* TARGET_FLAVOUR_FPGA */ 501 502 #define PLAT_ARM_RUN_UART_BASE TC_UART0 503 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 504 505 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ TC_UARTCLK 506 #define PLAT_ARM_RUN_UART_CLK_IN_HZ TC_UARTCLK 507 508 #define NCI_BASE_ADDR UL(0x4F000000) 509 #if (TARGET_PLATFORM == 3) && defined(TARGET_FLAVOUR_FPGA) 510 #define MCN_ADDRESS_SPACE_SIZE 0x00120000 511 #else 512 #define MCN_ADDRESS_SPACE_SIZE 0x00130000 513 #endif /* (TARGET_PLATFORM == 3) && defined(TARGET_FLAVOUR_FPGA) */ 514 #if TARGET_PLATFORM == 3 515 #define MCN_OFFSET_IN_NCI 0x00C90000 516 #else /* TARGET_PLATFORM == 4 */ 517 #ifdef TARGET_FLAVOUR_FPGA 518 #define MCN_OFFSET_IN_NCI 0x00420000 519 #else 520 #define MCN_OFFSET_IN_NCI 0x00D80000 521 #endif /* TARGET_FLAVOUR_FPGA */ 522 #endif /* TARGET_PLATFORM == 3 */ 523 #define MCN_BASE_ADDR(n) (NCI_BASE_ADDR + MCN_OFFSET_IN_NCI + \ 524 ((n) * MCN_ADDRESS_SPACE_SIZE)) 525 #define MCN_PMU_OFFSET 0x000C4000 526 #define MCN_MICROARCH_OFFSET 0x000E4000 527 #define MCN_MICROARCH_BASE_ADDR(n) (MCN_BASE_ADDR(n) + \ 528 MCN_MICROARCH_OFFSET) 529 #define MCN_SCR_OFFSET 0x4 530 #define MCN_SCR_PMU_BIT 10 531 #if TARGET_PLATFORM == 3 532 #define MCN_INSTANCES 4 533 #else /* TARGET_PLATFORM == 4 */ 534 #define MCN_INSTANCES 8 535 #endif /* TARGET_PLATFORM == 3 */ 536 #define MCN_PMU_ADDR(n) (MCN_BASE_ADDR(n) + \ 537 MCN_PMU_OFFSET) 538 #define MCN_MPAM_NS_OFFSET 0x000D0000 539 #define MCN_MPAM_NS_BASE_ADDR(n) (MCN_BASE_ADDR(n) + MCN_MPAM_NS_OFFSET) 540 #define MCN_MPAM_S_OFFSET 0x000D4000 541 #define MCN_MPAM_S_BASE_ADDR(n) (MCN_BASE_ADDR(n) + MCN_MPAM_S_OFFSET) 542 #define MPAM_SLCCFG_CTL_OFFSET 0x00003018 543 #define SLC_RDALLOCMODE_SHIFT 8 544 #define SLC_RDALLOCMODE_MASK (3 << SLC_RDALLOCMODE_SHIFT) 545 #define SLC_WRALLOCMODE_SHIFT 12 546 #define SLC_WRALLOCMODE_MASK (3 << SLC_WRALLOCMODE_SHIFT) 547 548 #define SLC_DONT_ALLOC 0 549 #define SLC_ALWAYS_ALLOC 1 550 #define SLC_ALLOC_BUS_SIGNAL_ATTR 2 551 552 #define MCN_CONFIG_OFFSET 0x204 553 #define MCN_CONFIG_ADDR(n) (MCN_BASE_ADDR(n) + MCN_CONFIG_OFFSET) 554 #define MCN_CONFIG_SLC_PRESENT_BIT 3 555 556 #define MCN_MTU_OFFSET 0x44000 557 #define MCN_MTU_BASE_ADDR(n) (MCN_BASE_ADDR(n) + MCN_MTU_OFFSET) 558 #define MTU_TAG_ADDR_BASE_OFFSET 0x0 559 560 #define MCN_CRP_OFFSET 0x24000 561 #define MCN_CRP_BASE_ADDR(n) (MCN_BASE_ADDR(n) + MCN_CRP_OFFSET) 562 #define MCN_CRP_ARCH_STATE_REQ_OFFSET 0 563 #define MCN_CRP_ARCH_STATE_CUR_OFFSET 8 564 565 #define MCN_CONFIG_STATE 0 566 #define MCN_RUN_STATE 1 567 568 /* 569 * TC3 CPUs have the same definitions for: 570 * CORTEX_{A520|A725|X925}_CPUECTLR_EL1 571 * CORTEX_{A520|A725|X925}_CPUECTLR_EL1_EXTLLC_BIT 572 * Define the common macros for easier using. 573 */ 574 #define CPUECTLR_EL1 CORTEX_A520_CPUECTLR_EL1 575 #define CPUECTLR_EL1_EXTLLC_BIT CORTEX_A520_CPUECTLR_EL1_EXTLLC_BIT 576 577 #define CPUACTLR_CLUSTERPMUEN (ULL(1) << 12) 578 579 #endif /* PLATFORM_DEF_H */ 580