1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_nano.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Nano must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Nano supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "Arm C1-Nano needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue c1_nano 30 31workaround_reset_start c1_nano, ERRATUM(3392149), ERRATA_C1NANO_3392149 32 sysreg_bit_set C1_NANO_IMP_CPUACTLR3_EL1, BIT(39) 33workaround_reset_end c1_nano, ERRATUM(3392149) 34 35check_erratum_ls c1_nano, ERRATUM(3392149), CPU_REV(0, 0) 36 37workaround_reset_start c1_nano, ERRATUM(3437202), ERRATA_C1NANO_3437202 38 sysreg_bit_set C1_NANO_IMP_CPUACTLR_EL1, BIT(26) 39workaround_reset_end c1_nano, ERRATUM(3437202) 40 41check_erratum_ls c1_nano, ERRATUM(3437202), CPU_REV(0, 0) 42 43cpu_reset_func_start c1_nano 44 /* ---------------------------------------------------- 45 * Disable speculative loads 46 * ---------------------------------------------------- 47 */ 48 msr SSBS, xzr 49 /* model bug: not cleared on reset */ 50 sysreg_bit_clear C1_NANO_IMP_CPUPWRCTLR_EL1, \ 51 C1_NANO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 52 enable_mpmm 53cpu_reset_func_end c1_nano 54 55func c1_nano_core_pwr_dwn 56 /* --------------------------------------------------- 57 * Enable CPU power down bit in power control register 58 * --------------------------------------------------- 59 */ 60 sysreg_bit_toggle C1_NANO_IMP_CPUPWRCTLR_EL1, \ 61 C1_NANO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 62 isb 63 signal_pabandon_handled 64 ret 65endfunc c1_nano_core_pwr_dwn 66 67.section .rodata.c1_nano_regs, "aS" 68c1_nano_regs: /* The ASCII list of register names to be reported */ 69 .asciz "cpuectlr_el1", "" 70 71func c1_nano_cpu_reg_dump 72 adr x6, c1_nano_regs 73 mrs x8, C1_NANO_IMP_CPUECTLR_EL1 74 ret 75endfunc c1_nano_cpu_reg_dump 76 77declare_cpu_ops c1_nano, C1_NANO_MIDR, \ 78 c1_nano_reset_func, \ 79 c1_nano_core_pwr_dwn 80