1 /* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef C1_NANO_H 8 #define C1_NANO_H 9 10 #define C1_NANO_MIDR U(0x410FD8A0) 11 12 /******************************************************************************* 13 * CPU Extended Control register specific definitions 14 ******************************************************************************/ 15 #define C1_NANO_IMP_CPUECTLR_EL1 S3_0_C15_C1_4 16 17 /******************************************************************************* 18 * CPU Power Control register specific definitions 19 ******************************************************************************/ 20 #define C1_NANO_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7 21 #define C1_NANO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) 22 #define C1_NANO_IMP_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT U(7) 23 #define C1_NANO_IMP_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH U(3) 24 #define C1_NANO_IMP_CPUPWRCTLR_EL1_WFE_RET_CTRL_BIT U(0) 25 #define C1_NANO_IMP_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT U(4) 26 #define C1_NANO_IMP_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH U(3) 27 #define C1_NANO_IMP_CPUPWRCTLR_EL1_WFI_RET_CTRL_BIT U(0) 28 29 /******************************************************************************* 30 * CPU Auxiliary Control register specific definitions 31 ******************************************************************************/ 32 #define C1_NANO_IMP_CPUACTLR_EL1 S3_0_C15_C1_0 33 #define C1_NANO_IMP_CPUACTLR3_EL1 S3_0_C15_C1_2 34 35 /******************************************************************************* 36 * CPU Instruction Private register specific definitions 37 ******************************************************************************/ 38 #define C1_NANO_IMP_CPUPSELR_EL3 S3_6_C15_C8_0 39 #define C1_NANO_IMP_CPUPCR_EL3 S3_6_C15_C8_1 40 #define C1_NANO_IMP_CPUPOR_EL3 S3_6_C15_C8_2 41 #define C1_NANO_IMP_CPUPMR_EL3 S3_6_C15_C8_3 42 43 #endif /* C1_NANO_H */ 44