1/* 2 * Copyright (c) 2024-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_premium.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Premium must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Premium supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "Arm C1-Premium needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue c1_premium 30 31 /* --------------------------------------------------------------- 32 * CVE-2024-7881 is mitigated for C1-Premium using erratum 3651221 33 * workaround by disabling the affected prefetcher setting 34 * CPUACTLR6_EL1[41]. 35 * --------------------------------------------------------------- 36 */ 37workaround_reset_start c1_premium, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 38 sysreg_bit_set C1_PREMIUM_CPUACTLR6_EL1, BIT(41) 39workaround_reset_end c1_premium, CVE(2024, 7881) 40 41check_erratum_ls c1_premium, CVE(2024, 7881), CPU_REV(0, 0) 42 43workaround_runtime_start c1_premium, ERRATUM(3324333), ERRATA_C1PREMIUM_3324333 44 speculation_barrier 45workaround_runtime_end c1_premium, ERRATUM(3324333) 46 47check_erratum_ls c1_premium, ERRATUM(3324333), CPU_REV(0, 0) 48 49workaround_reset_start c1_premium, ERRATUM(3502731), ERRATA_C1PREMIUM_3502731 50 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR4_EL1, BIT(23) 51workaround_reset_end c1_premium, ERRATUM(3502731) 52 53check_erratum_ls c1_premium, ERRATUM(3502731), CPU_REV(0, 0) 54 55workaround_reset_start c1_premium, ERRATUM(3651221), ERRATA_C1PREMIUM_3651221 56 sysreg_bit_set C1_PREMIUM_CPUACTLR6_EL1, BIT(41) 57workaround_reset_end c1_premium, ERRATUM(3651221) 58 59check_erratum_ls c1_premium, ERRATUM(3651221), CPU_REV(0, 0) 60 61workaround_reset_start c1_premium, ERRATUM(3684152), ERRATA_C1PREMIUM_3684152 62 sysreg_bitfield_insert C1_PREMIUM_IMP_CPUACTLR_EL1, C1_PREMIUM_IMP_CPUACTLR_EL1_LOAD_BIT, \ 63 C1_PREMIUM_IMP_CPUACTLR_EL1_LOAD_SHIFT, C1_PREMIUM_IMP_CPUACTLR_EL1_LOAD_WIDTH 64workaround_reset_end c1_premium, ERRATUM(3684152) 65 66check_erratum_ls c1_premium, ERRATUM(3684152), CPU_REV(0, 0) 67 68workaround_reset_start c1_premium, ERRATUM(3705939), ERRATA_C1PREMIUM_3705939 69 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR_EL1, BIT(48) 70workaround_reset_end c1_premium, ERRATUM(3705939) 71 72check_erratum_ls c1_premium, ERRATUM(3705939), CPU_REV(1, 0) 73 74workaround_reset_start c1_premium, ERRATUM(3815514), ERRATA_C1PREMIUM_3815514 75 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR5_EL1, BIT(13) 76workaround_reset_end c1_premium, ERRATUM(3815514) 77 78check_erratum_ls c1_premium, ERRATUM(3815514), CPU_REV(1, 0) 79 80workaround_reset_start c1_premium, ERRATUM(3865171), ERRATA_C1PREMIUM_3865171 81 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR2_EL1, BIT(22) 82workaround_reset_end c1_premium, ERRATUM(3865171) 83 84check_erratum_ls c1_premium, ERRATUM(3865171), CPU_REV(1, 0) 85 86workaround_reset_start c1_premium, ERRATUM(3926381), ERRATA_C1PREMIUM_3926381 87 /* Convert WFx to NOP */ 88 ldr x0,=0x0 89 msr C1_PREMIUM_IMP_CPUPSELR_EL3, x0 90 ldr x0,=0xD503205f 91 msr C1_PREMIUM_IMP_CPUPOR_EL3, x0 92 ldr x0,=0xFFFFFFDF 93 msr C1_PREMIUM_IMP_CPUPMR_EL3, x0 94 ldr x0,=0x1000002043ff 95 msr C1_PREMIUM_IMP_CPUPCR_EL3, x0 96 97 /* Convert WFxT to NOP */ 98 ldr x0,=0x1 99 msr C1_PREMIUM_IMP_CPUPSELR_EL3, x0 100 ldr x0,=0xD5031000 101 msr C1_PREMIUM_IMP_CPUPOR_EL3, x0 102 ldr x0,=0xFFFFFFC0 103 msr C1_PREMIUM_IMP_CPUPMR_EL3, x0 104 ldr x0,=0x1000002043ff 105 msr C1_PREMIUM_IMP_CPUPCR_EL3, x0 106 isb 107workaround_reset_end c1_premium, ERRATUM(3926381) 108 109check_erratum_range c1_premium, ERRATUM(3926381), CPU_REV(1, 0), CPU_REV(1, 0) 110 111workaround_reset_start c1_premium, ERRATUM(4102704), ERRATA_C1PREMIUM_4102704 112 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR4_EL1, BIT(23) 113workaround_reset_end c1_premium, ERRATUM(4102704) 114 115check_erratum_ls c1_premium, ERRATUM(4102704), CPU_REV(1, 0) 116 117cpu_reset_func_start c1_premium 118 /* Disable speculative loads */ 119 msr SSBS, xzr 120 apply_erratum c1_premium, ERRATUM(3324333), ERRATA_C1PREMIUM_3324333 121 enable_mpmm 122cpu_reset_func_end c1_premium 123 124func c1_premium_core_pwr_dwn 125 /* --------------------------------------------------- 126 * Flip CPU power down bit in power control register. 127 * It will be set on powerdown and cleared on wakeup. 128 * --------------------------------------------------- 129 */ 130 sysreg_bit_toggle C1_PREMIUM_IMP_CPUPWRCTLR_EL1, \ 131 C1_PREMIUM_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 132 isb 133 signal_pabandon_handled 134 ret 135endfunc c1_premium_core_pwr_dwn 136 137.section .rodata.c1_premium_regs, "aS" 138c1_premium_regs: /* The ASCII list of register names to be reported */ 139 .asciz "cpuectlr_el1", "" 140 141func c1_premium_cpu_reg_dump 142 adr x6, c1_premium_regs 143 mrs x8, C1_PREMIUM_IMP_CPUECTLR_EL1 144 ret 145endfunc c1_premium_cpu_reg_dump 146 147declare_cpu_ops c1_premium, C1_PREMIUM_MIDR, \ 148 c1_premium_reset_func, \ 149 c1_premium_core_pwr_dwn 150