1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_pro.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Pro must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Pro supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "Arm C1-Pro needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue c1_pro 30 31 /* ----------------------------------------------------------- 32 * CVE-2024-7881 is mitigated for C1-Pro using erratum 3684268 33 * workaround by disabling the affected prefetcher 34 * via IMP_CPUECTLR_EL1[49]. 35 * ----------------------------------------------------------- 36 */ 37workaround_reset_start c1_pro, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 38 sysreg_bit_set C1_PRO_IMP_CPUECTLR_EL1, BIT(49) 39 dsb sy 40workaround_reset_end c1_pro, CVE(2024, 7881) 41 42check_erratum_ls c1_pro, CVE(2024, 7881), CPU_REV(1, 0) 43 44workaround_runtime_start c1_pro, ERRATUM(3338470), ERRATA_C1PRO_3338470 45 speculation_barrier 46workaround_runtime_end c1_pro, ERRATUM(3338470) 47 48check_erratum_ls c1_pro, ERRATUM(3338470), CPU_REV(0, 0) 49 50workaround_reset_start c1_pro, ERRATUM(3362007), ERRATA_C1PRO_3362007 51 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(27) 52workaround_reset_end c1_pro, ERRATUM(3362007) 53 54check_erratum_ls c1_pro, ERRATUM(3362007), CPU_REV(0, 0) 55 56workaround_reset_start c1_pro, ERRATUM(3684268), ERRATA_C1PRO_3684268 57 sysreg_bit_set C1_PRO_IMP_CPUECTLR2_EL1, BIT(49) 58 dsb sy 59workaround_reset_end c1_pro, ERRATUM(3684268) 60 61check_erratum_ls c1_pro, ERRATUM(3684268), CPU_REV(1, 0) 62 63workaround_reset_start c1_pro, ERRATUM(3694158), ERRATA_C1PRO_3694158 64 mov x0, #5 65 msr C1_PRO_IMP_CPUPSELR_EL3, x0 66 isb 67 ldr x0, =0xd503329f 68 msr C1_PRO_IMP_CPUPOR_EL3, x0 69 ldr x0, =0xfffff3ff 70 msr C1_PRO_IMP_CPUPMR_EL3, x0 71 mov x1, #0 72 orr x1, x1, #1<<0 73 orr x1, x1, #3<<4 74 orr x1, x1, #0xf<<6 75 orr x1, x1, #1<<22 76 orr x1, x1, #1<<32 77 msr C1_PRO_IMP_CPUPCR_EL3, x1 78workaround_reset_end c1_pro, ERRATUM(3694158) 79 80check_erratum_ls c1_pro, ERRATUM(3694158), CPU_REV(1, 1) 81 82workaround_reset_start c1_pro, ERRATUM(3706576), ERRATA_C1PRO_3706576 83 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(37) 84workaround_reset_end c1_pro, ERRATUM(3706576) 85 86check_erratum_ls c1_pro, ERRATUM(3706576), CPU_REV(1, 0) 87 88add_erratum_entry c1_pro, ERRATUM(3300099), ERRATA_C1PRO_3300099 89.global check_erratum_c1_pro_3300099 90check_erratum_ls c1_pro, ERRATUM(3300099), CPU_REV(1, 0) 91 92cpu_reset_func_start c1_pro 93 /* ---------------------------------------------------- 94 * Disable speculative loads 95 * ---------------------------------------------------- 96 */ 97 msr SSBS, xzr 98 apply_erratum c1_pro, ERRATUM(3338470), ERRATA_C1PRO_3338470 99 /* model bug: not cleared on reset */ 100 sysreg_bit_clear C1_PRO_IMP_CPUPWRCTLR_EL1, \ 101 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 102 enable_mpmm 103cpu_reset_func_end c1_pro 104 105 /* ---------------------------------------------------- 106 * HW will do the cache maintenance while powering down 107 * ---------------------------------------------------- 108 */ 109func c1_pro_core_pwr_dwn 110 /* --------------------------------------------------- 111 * Flip CPU power down bit in power control register. 112 * It will be set on powerdown and cleared on wakeup 113 * --------------------------------------------------- 114 */ 115 sysreg_bit_toggle C1_PRO_IMP_CPUPWRCTLR_EL1, \ 116 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 117 isb 118 signal_pabandon_handled 119 ret 120endfunc c1_pro_core_pwr_dwn 121 122 /* --------------------------------------------- 123 * This function provides Arm C1-Pro specific 124 * register information for crash reporting. 125 * It needs to return with x6 pointing to 126 * a list of register names in ascii and 127 * x8 - x15 having values of registers to be 128 * reported. 129 * --------------------------------------------- 130 */ 131.section .rodata.c1_pro_regs, "aS" 132c1_pro_regs: /* The ASCII list of register names to be reported */ 133 .asciz "imp_cpuectlr_el1", "" 134 135func c1_pro_cpu_reg_dump 136 adr x6, c1_pro_regs 137 mrs x8, C1_PRO_IMP_CPUECTLR_EL1 138 ret 139endfunc c1_pro_cpu_reg_dump 140 141declare_cpu_ops c1_pro, C1_PRO_MIDR, \ 142 c1_pro_reset_func, \ 143 c1_pro_core_pwr_dwn 144