1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_pro.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Pro must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Pro supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "Arm C1-Pro needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue c1_pro 30 31 /* ----------------------------------------------------------- 32 * CVE-2024-7881 is mitigated for C1-Pro using erratum 3684268 33 * workaround by disabling the affected prefetcher 34 * via IMP_CPUECTLR_EL1[49]. 35 * ----------------------------------------------------------- 36 */ 37workaround_reset_start c1_pro, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 38 sysreg_bit_set C1_PRO_IMP_CPUECTLR_EL1, BIT(49) 39 dsb sy 40workaround_reset_end c1_pro, CVE(2024, 7881) 41 42check_erratum_ls c1_pro, CVE(2024, 7881), CPU_REV(1, 0) 43 44workaround_runtime_start c1_pro, ERRATUM(3338470), ERRATA_C1PRO_3338470 45 speculation_barrier 46workaround_runtime_end c1_pro, ERRATUM(3338470) 47 48check_erratum_ls c1_pro, ERRATUM(3338470), CPU_REV(0, 0) 49 50workaround_reset_start c1_pro, ERRATUM(3362007), ERRATA_C1PRO_3362007 51 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(27) 52workaround_reset_end c1_pro, ERRATUM(3362007) 53 54check_erratum_ls c1_pro, ERRATUM(3362007), CPU_REV(0, 0) 55 56workaround_reset_start c1_pro, ERRATUM(3619847), ERRATA_C1PRO_3619847 57 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(42) 58workaround_reset_end c1_pro, ERRATUM(3619847) 59 60check_erratum_ls c1_pro, ERRATUM(3619847), CPU_REV(0, 0) 61 62workaround_reset_start c1_pro, ERRATUM(3684268), ERRATA_C1PRO_3684268 63 sysreg_bit_set C1_PRO_IMP_CPUECTLR2_EL1, BIT(49) 64 dsb sy 65workaround_reset_end c1_pro, ERRATUM(3684268) 66 67check_erratum_ls c1_pro, ERRATUM(3684268), CPU_REV(1, 0) 68 69workaround_runtime_start c1_pro, ERRATUM(3686597), ERRATA_C1PRO_3686597 70 /* check if sme feature supported */ 71 is_feat_sme_present_asm x1 72 beq 1f 73 74 sysreg_bit_set C1_PRO_IMP_CPUECTLR_EL1, BIT(57) 75 dsb sy 76 771: 78workaround_runtime_end c1_pro, ERRATUM(3686597) 79 80check_erratum_ls c1_pro, ERRATUM(3686597), CPU_REV(1, 0) 81 82workaround_reset_start c1_pro, ERRATUM(3694158), ERRATA_C1PRO_3694158 83 mov x0, #5 84 msr C1_PRO_IMP_CPUPSELR_EL3, x0 85 isb 86 ldr x0, =0xd503329f 87 msr C1_PRO_IMP_CPUPOR_EL3, x0 88 ldr x0, =0xfffff3ff 89 msr C1_PRO_IMP_CPUPMR_EL3, x0 90 mov x1, #0 91 orr x1, x1, #1<<0 92 orr x1, x1, #3<<4 93 orr x1, x1, #0xf<<6 94 orr x1, x1, #1<<22 95 orr x1, x1, #1<<32 96 msr C1_PRO_IMP_CPUPCR_EL3, x1 97workaround_reset_end c1_pro, ERRATUM(3694158) 98 99check_erratum_ls c1_pro, ERRATUM(3694158), CPU_REV(1, 1) 100 101workaround_reset_start c1_pro, ERRATUM(3706576), ERRATA_C1PRO_3706576 102 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(37) 103workaround_reset_end c1_pro, ERRATUM(3706576) 104 105check_erratum_ls c1_pro, ERRATUM(3706576), CPU_REV(1, 0) 106 107add_erratum_entry c1_pro, ERRATUM(3300099), ERRATA_C1PRO_3300099 108.global check_erratum_c1_pro_3300099 109check_erratum_ls c1_pro, ERRATUM(3300099), CPU_REV(1, 0) 110 111cpu_reset_func_start c1_pro 112 /* ---------------------------------------------------- 113 * Disable speculative loads 114 * ---------------------------------------------------- 115 */ 116 msr SSBS, xzr 117 apply_erratum c1_pro, ERRATUM(3338470), ERRATA_C1PRO_3338470 118 /* model bug: not cleared on reset */ 119 sysreg_bit_clear C1_PRO_IMP_CPUPWRCTLR_EL1, \ 120 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 121 enable_mpmm 122cpu_reset_func_end c1_pro 123 124 /* ---------------------------------------------------- 125 * HW will do the cache maintenance while powering down 126 * ---------------------------------------------------- 127 */ 128func c1_pro_core_pwr_dwn 129 /* --------------------------------------------------- 130 * Flip CPU power down bit in power control register. 131 * It will be set on powerdown and cleared on wakeup 132 * --------------------------------------------------- 133 */ 134 apply_erratum c1_pro, ERRATUM(3686597), ERRATA_C1PRO_3686597 135 sysreg_bit_toggle C1_PRO_IMP_CPUPWRCTLR_EL1, \ 136 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 137 isb 138 signal_pabandon_handled 139 ret 140endfunc c1_pro_core_pwr_dwn 141 142 /* --------------------------------------------- 143 * This function provides Arm C1-Pro specific 144 * register information for crash reporting. 145 * It needs to return with x6 pointing to 146 * a list of register names in ascii and 147 * x8 - x15 having values of registers to be 148 * reported. 149 * --------------------------------------------- 150 */ 151.section .rodata.c1_pro_regs, "aS" 152c1_pro_regs: /* The ASCII list of register names to be reported */ 153 .asciz "imp_cpuectlr_el1", "" 154 155func c1_pro_cpu_reg_dump 156 adr x6, c1_pro_regs 157 mrs x8, C1_PRO_IMP_CPUECTLR_EL1 158 ret 159endfunc c1_pro_cpu_reg_dump 160 161declare_cpu_ops c1_pro, C1_PRO_MIDR, \ 162 c1_pro_reset_func, \ 163 c1_pro_core_pwr_dwn 164