1/* 2 * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue neoverse_v3 26 27.global check_erratum_neoverse_v3_3701767 28 29workaround_reset_start neoverse_v3, ERRATUM(2970647), ERRATA_V3_2970647 30 /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ 31 ldr x0, =0x1 32 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ 33 ldr x0, =0xd5380000 34 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ 35 ldr x0, =0xFFFFFF40 36 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ 37 ldr x0, =0x000080010033f 38 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ 39 isb 40workaround_reset_end neoverse_v3, ERRATUM(2970647) 41 42check_erratum_ls neoverse_v3, ERRATUM(2970647), CPU_REV(0, 0) 43 44workaround_runtime_start neoverse_v3, ERRATUM(3312417), ERRATA_V3_3312417 45 speculation_barrier 46workaround_runtime_end neoverse_v3, ERRATUM(3312417) 47 48check_erratum_ls neoverse_v3, ERRATUM(3312417), CPU_REV(0, 1) 49 50workaround_reset_start neoverse_v3, ERRATUM(3696307), ERRATA_V3_3696307 51 sysreg_bit_set NEOVERSE_V3_CPUACTLR6_EL1, BIT(41) 52workaround_reset_end neoverse_v3, ERRATUM(3696307) 53 54check_erratum_ls neoverse_v3, ERRATUM(3696307), CPU_REV(0, 1) 55 56add_erratum_entry neoverse_v3, ERRATUM(3701767), ERRATA_V3_3701767 57 58check_erratum_ls neoverse_v3, ERRATUM(3701767), CPU_REV(0, 2) 59 60workaround_reset_start neoverse_v3, ERRATUM(3734562), ERRATA_V3_3734562 61 mov x0, #2 62 msr NEOVERSE_V3_CPUPSELR_EL3, x0 63 ldr x0, =0xD503225F 64 msr NEOVERSE_V3_CPUPOR_EL3, x0 65 mov x0, 0xFFFFFFFF 66 msr NEOVERSE_V3_CPUPMR_EL3, x0 67 ldr x0, =0x404003FD 68 msr NEOVERSE_V3_CPUPCR_EL3, x0 69workaround_reset_end neoverse_v3, ERRATUM(3734562) 70 71check_erratum_ls neoverse_v3, ERRATUM(3734562), CPU_REV(0, 1) 72 73workaround_reset_start neoverse_v3, ERRATUM(3782181), ERRATA_V3_3782181 74 /* Disable retention control for WFI and WFE. */ 75 mrs x0, NEOVERSE_V3_CPUPWRCTLR_EL1 76 bfi x0, xzr, #NEOVERSE_V3_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT, \ 77 #NEOVERSE_V3_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH 78 bfi x0, xzr, #NEOVERSE_V3_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT, \ 79 #NEOVERSE_V3_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH 80 msr NEOVERSE_V3_CPUPWRCTLR_EL1, x0 81workaround_reset_end neoverse_v3, ERRATUM(3782181) 82 83check_erratum_range neoverse_v3, ERRATUM(3782181), CPU_REV(0, 1), \ 84 CPU_REV(0, 1) 85 86workaround_reset_start neoverse_v3, ERRATUM(3864536), ERRATA_V3_3864536 87 sysreg_bit_set NEOVERSE_V3_CPUACTLR2_EL1, BIT(22) 88workaround_reset_end neoverse_v3, ERRATUM(3864536) 89 90check_erratum_ls neoverse_v3, ERRATUM(3864536), CPU_REV(0, 2) 91 92workaround_reset_start neoverse_v3, ERRATUM(3878291), ERRATA_V3_3878291 93 sysreg_bit_set NEOVERSE_V3_CPUACTLR4_EL1, BIT(57) 94workaround_reset_end neoverse_v3, ERRATUM(3878291) 95 96check_erratum_ls neoverse_v3, ERRATUM(3878291), CPU_REV(0, 2) 97 98/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 99workaround_reset_start neoverse_v3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 100 sysreg_bit_set NEOVERSE_V3_CPUECTLR_EL1, BIT(46) 101workaround_reset_end neoverse_v3, CVE(2024, 5660) 102 103check_erratum_ls neoverse_v3, CVE(2024, 5660), CPU_REV(0, 1) 104 105 /* ---------------------------------------------------------------- 106 * CVE-2024-7881 is mitigated for Neoverse-V3 / Neoverse-V3AE 107 * using erratum 3696307 workaround by disabling the 108 * affected prefetcher setting CPUACTLR6_EL1[41]. 109 * ---------------------------------------------------------------- 110 */ 111workaround_reset_start neoverse_v3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 112 sysreg_bit_set NEOVERSE_V3_CPUACTLR6_EL1, BIT(41) 113workaround_reset_end neoverse_v3, CVE(2024, 7881) 114 115check_erratum_ls neoverse_v3, CVE(2024, 7881), CPU_REV(0, 1) 116 117 /* --------------------------------------------- 118 * HW will do the cache maintenance while powering down 119 * --------------------------------------------- 120 */ 121func neoverse_v3_core_pwr_dwn 122 /* --------------------------------------------- 123 * Enable CPU power down bit in power control register 124 * --------------------------------------------- 125 */ 126 sysreg_bit_set NEOVERSE_V3_CPUPWRCTLR_EL1, \ 127 NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 128 129 isb 130 ret 131endfunc neoverse_v3_core_pwr_dwn 132 133cpu_reset_func_start neoverse_v3 134 /* Disable speculative loads */ 135 msr SSBS, xzr 136 apply_erratum neoverse_v3, ERRATUM(3312417), ERRATA_V3_3312417 137cpu_reset_func_end neoverse_v3 138 139 /* --------------------------------------------- 140 * This function provides Neoverse V3 specific 141 * register information for crash reporting. 142 * It needs to return with x6 pointing to 143 * a list of register names in ascii and 144 * x8 - x15 having values of registers to be 145 * reported. 146 * --------------------------------------------- 147 */ 148.section .rodata.neoverse_v3_regs, "aS" 149neoverse_v3_regs: /* The ascii list of register names to be reported */ 150 .asciz "cpuectlr_el1", "" 151 152func neoverse_v3_cpu_reg_dump 153 adr x6, neoverse_v3_regs 154 mrs x8, NEOVERSE_V3_CPUECTLR_EL1 155 ret 156endfunc neoverse_v3_cpu_reg_dump 157 158declare_cpu_ops neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \ 159 neoverse_v3_reset_func, \ 160 neoverse_v3_core_pwr_dwn 161 162declare_cpu_ops neoverse_v3, NEOVERSE_V3_MIDR, \ 163 neoverse_v3_reset_func, \ 164 neoverse_v3_core_pwr_dwn 165