1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_nano.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Nano must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Nano supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "Arm C1-Nano needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue c1_nano 30 31workaround_reset_start c1_nano, ERRATUM(3392149), ERRATA_C1NANO_3392149 32 sysreg_bit_set C1_NANO_IMP_CPUACTLR3_EL1, BIT(39) 33workaround_reset_end c1_nano, ERRATUM(3392149) 34 35check_erratum_ls c1_nano, ERRATUM(3392149), CPU_REV(0, 0) 36 37cpu_reset_func_start c1_nano 38 /* ---------------------------------------------------- 39 * Disable speculative loads 40 * ---------------------------------------------------- 41 */ 42 msr SSBS, xzr 43 /* model bug: not cleared on reset */ 44 sysreg_bit_clear C1_NANO_IMP_CPUPWRCTLR_EL1, \ 45 C1_NANO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 46 enable_mpmm 47cpu_reset_func_end c1_nano 48 49func c1_nano_core_pwr_dwn 50 /* --------------------------------------------------- 51 * Enable CPU power down bit in power control register 52 * --------------------------------------------------- 53 */ 54 sysreg_bit_toggle C1_NANO_IMP_CPUPWRCTLR_EL1, \ 55 C1_NANO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 56 isb 57 signal_pabandon_handled 58 ret 59endfunc c1_nano_core_pwr_dwn 60 61.section .rodata.c1_nano_regs, "aS" 62c1_nano_regs: /* The ASCII list of register names to be reported */ 63 .asciz "cpuectlr_el1", "" 64 65func c1_nano_cpu_reg_dump 66 adr x6, c1_nano_regs 67 mrs x8, C1_NANO_IMP_CPUECTLR_EL1 68 ret 69endfunc c1_nano_cpu_reg_dump 70 71declare_cpu_ops c1_nano, C1_NANO_MIDR, \ 72 c1_nano_reset_func, \ 73 c1_nano_core_pwr_dwn 74