1 /* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_X925_H 8 #define CORTEX_X925_H 9 10 #define CORTEX_X925_MIDR U(0x410FD850) 11 12 /******************************************************************************* 13 * CPU Extended Control register specific definitions 14 ******************************************************************************/ 15 #define CORTEX_X925_CPUECTLR_EL1 S3_0_C15_C1_4 16 #define CORTEX_X925_CPUECTLR_EL1_EXTLLC_BIT U(0) 17 18 /******************************************************************************* 19 * CPU Power Control register specific definitions 20 ******************************************************************************/ 21 #define CORTEX_X925_CPUPWRCTLR_EL1 S3_0_C15_C2_7 22 #define CORTEX_X925_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 23 24 /******************************************************************************* 25 * CPU Auxiliary control register specific definitions 26 ******************************************************************************/ 27 #define CORTEX_X925_CPUACTLR4_EL1 S3_0_C15_C1_3 28 #define CORTEX_X925_CPUACTLR4_EL1_BHB_BIT U(3) 29 #define CORTEX_X925_CPUACTLR4_EL1_BHB_SHIFT U(10) 30 #define CORTEX_X925_CPUACTLR4_EL1_BHB_WIDTH U(2) 31 #define CORTEX_X925_CPUACTLR5_EL1 S3_0_C15_C8_0 32 #define CORTEX_X925_CPUACTLR6_EL1 S3_0_C15_C8_1 33 34 #ifndef __ASSEMBLER__ 35 long check_erratum_cortex_x925_3701747(long cpu_rev); 36 #endif /* __ASSEMBLER__ */ 37 38 #endif /* CORTEX_X925_H */ 39