1/* 2 * Copyright (c) 2024-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a720_ae.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A720AE must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-A720AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24cpu_reset_prologue cortex_a720_ae 25 26.global check_erratum_cortex_a720_ae_3699562 27 28workaround_runtime_start cortex_a720_ae, ERRATUM(3456103), ERRATA_A720_AE_3456103 29 speculation_barrier 30workaround_runtime_end cortex_a720_ae, ERRATUM(3456103) 31 32check_erratum_ls cortex_a720_ae, ERRATUM(3456103), CPU_REV(0, 1) 33 34add_erratum_entry cortex_a720_ae, ERRATUM(3699562), ERRATA_A720_AE_3699562 35 36check_erratum_ls cortex_a720_ae, ERRATUM(3699562), CPU_REV(0, 0) 37 38cpu_reset_func_start cortex_a720_ae 39 /* Disable speculative loads */ 40 msr SSBS, xzr 41 apply_erratum cortex_a720_ae, ERRATUM(3456103), ERRATA_A720_AE_3456103 42 43 enable_mpmm 44cpu_reset_func_end cortex_a720_ae 45 46 /* ---------------------------------------------------- 47 * HW will do the cache maintenance while powering down 48 * ---------------------------------------------------- 49 */ 50func cortex_a720_ae_core_pwr_dwn 51 /* --------------------------------------------------- 52 * Enable CPU power down bit in power control register 53 * --------------------------------------------------- 54 */ 55 sysreg_bit_set CORTEX_A720_AE_CPUPWRCTLR_EL1, CORTEX_A720_AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 56 57 isb 58 ret 59endfunc cortex_a720_ae_core_pwr_dwn 60 61 /* --------------------------------------------- 62 * This function provides Cortex-A720AE specific 63 * register information for crash reporting. 64 * It needs to return with x6 pointing to 65 * a list of register names in ascii and 66 * x8 - x15 having values of registers to be 67 * reported. 68 * --------------------------------------------- 69 */ 70.section .rodata.cortex_a720_ae_regs, "aS" 71cortex_a720_ae_regs: /* The ascii list of register names to be reported */ 72 .asciz "cpuectlr_el1", "" 73 74func cortex_a720_ae_cpu_reg_dump 75 adr x6, cortex_a720_ae_regs 76 mrs x8, CORTEX_A720_AE_CPUECTLR_EL1 77 ret 78endfunc cortex_a720_ae_cpu_reg_dump 79 80declare_cpu_ops cortex_a720_ae, CORTEX_A720_AE_MIDR, \ 81 cortex_a720_ae_reset_func, \ 82 cortex_a720_ae_core_pwr_dwn 83