xref: /rk3399_ARM-atf/include/lib/cpus/aarch64/c1_pro.h (revision 740b3bb26ec1a8f7806f8031e9a089d4f7bc3626)
1 /*
2  * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef C1_PRO_H
8 #define C1_PRO_H
9 
10 #include <lib/utils_def.h>
11 
12 #define C1_PRO_MIDR				        U(0x410FD8B0)
13 
14 /*******************************************************************************
15  * CPU Generic System Control register specific definitions
16  ******************************************************************************/
17 #define C1_PRO_IMP_CPUACTLR2_EL1			S3_0_C15_C1_1
18 #define C1_PRO_IMP_CPUPSELR_EL3				S3_6_C15_C8_0
19 #define C1_PRO_IMP_CPUPCR_EL3				S3_6_C15_C8_1
20 #define C1_PRO_IMP_CPUPOR_EL3				S3_6_C15_C8_2
21 #define C1_PRO_IMP_CPUPMR_EL3				S3_6_C15_C8_3
22 
23 /*******************************************************************************
24  * CPU Extended Control register specific definitions
25  ******************************************************************************/
26 #define C1_PRO_IMP_CPUECTLR_EL1				S3_0_C15_C1_4
27 #define C1_PRO_CPUECTLR2_EL1_EXTLLC_BIT			U(10)
28 #define C1_PRO_IMP_CPUECTLR2_EL1			S3_0_C15_C1_5
29 
30 /*******************************************************************************
31  * CPU Power Control register specific definitions
32  ******************************************************************************/
33 #define C1_PRO_IMP_CPUPWRCTLR_EL1			S3_0_C15_C2_7
34 #define C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT	U(1)
35 
36 #ifndef __ASSEMBLER__
37 long check_erratum_c1_pro_3300099(long cpu_rev);
38 #endif /* __ASSEMBLER__ */
39 
40 #endif /* C1_PRO_H */
41