1/* 2 * Copyright (c) 2023-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#define GIC_CTRL_ADDR 30000000 8#define GIC_GICR_OFFSET 0x1000000 9#define UART_OFFSET 0x10000 10/* 1440x3200@120 framebuffer */ 11#define LCD_TIMING_CLK 836000000 12#define LCD_TIMING \ 13 clock-frequency = <LCD_TIMING_CLK>; \ 14 hactive = <1440>; \ 15 vactive = <3200>; \ 16 hfront-porch = <136>; \ 17 hback-porch = <296>; \ 18 hsync-len = <160>; \ 19 vfront-porch = <3>; \ 20 vback-porch = <217>; \ 21 vsync-len = <10> 22 23/ { 24 chosen { 25 stdout-path = "serial0:38400n8"; 26 }; 27 28#if TC_FPGA_FS_IMG_IN_RAM 29 reserved-memory { 30 phram { 31 /* 32 * starting from base of DRAM2 reserve some memory 33 * android image will be side loaded to this location 34 */ 35 reg = <HI(TC_DRAM2_BASE) LO(TC_DRAM2_BASE) 36 HI(ANDROID_FS_SIZE) LO(ANDROID_FS_SIZE)>; 37 no-map; 38 }; 39 }; 40#endif /* TC_FPGA_FS_IMG_IN_RAM */ 41 42 ethernet: ethernet@ETHERNET_ADDR { 43 compatible = "smsc,lan9115"; 44 phy-mode = "mii"; 45 }; 46 47 mmci: mmci@MMC_ADDR { 48 non-removable; 49 }; 50}; 51