1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9USE_GIC_DRIVER := 2 10 11JUNO_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \ 12 plat/arm/common/arm_cci.c 13 14JUNO_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 15 plat/arm/board/juno/juno_security.c \ 16 plat/arm/board/juno/juno_trng.c \ 17 plat/arm/common/arm_tzc400.c 18 19ifneq (${ENABLE_STACK_PROTECTOR}, 0) 20JUNO_SECURITY_SOURCES += plat/arm/board/juno/juno_stack_protector.c 21endif 22 23# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the 24# SCP during power management operations and for SCP RAM Firmware transfer. 25CSS_USE_SCMI_SDS_DRIVER := 1 26 27PLAT_INCLUDES := -Iplat/arm/board/juno/include 28 29PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/${ARCH}/juno_helpers.S \ 30 plat/arm/board/juno/juno_common.c 31 32ifeq (${SPMC_AT_EL3}, 1) 33PLAT_BL_COMMON_SOURCES += plat/arm/board/juno/juno_el3_spmc.c 34endif 35 36ifeq (${HOB_LIST}, 1) 37include lib/hob/hob.mk 38endif 39 40# Flag to enable support for AArch32 state on JUNO 41JUNO_AARCH32_EL3_RUNTIME := 0 42$(eval $(call assert_boolean,JUNO_AARCH32_EL3_RUNTIME)) 43$(eval $(call add_define,JUNO_AARCH32_EL3_RUNTIME)) 44 45# Flag to enable support for TZMP1 on JUNO 46JUNO_TZMP1 := 0 47$(eval $(call assert_boolean,JUNO_TZMP1)) 48ifeq (${JUNO_TZMP1}, 1) 49 ifeq (${ETHOSN_NPU_TZMP1},1) 50 $(error JUNO_TZMP1 cannot be used together with ETHOSN_NPU_TZMP1) 51 else 52 $(eval $(call add_define,JUNO_TZMP1)) 53 endif 54endif 55 56TRNG_SUPPORT := 1 57 58ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 59# Include BL32 in FIP 60NEED_BL32 := yes 61# BL31 is not required 62override BL31_SOURCES = 63 64# The BL32 needs to be built separately invoking the AARCH32 compiler and 65# be specifed via `BL32` build option. 66 ifneq (${ARCH}, aarch32) 67 override BL32_SOURCES = 68 endif 69else 70 ifeq (${ARCH}, aarch32) 71 $(error JUNO_AARCH32_EL3_RUNTIME has to be enabled to build BL32 for AArch32) 72 endif 73endif 74 75ifeq (${ARCH},aarch64) 76BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 77 lib/cpus/aarch64/cortex_a57.S \ 78 lib/cpus/aarch64/cortex_a72.S \ 79 plat/arm/board/juno/juno_err.c \ 80 plat/arm/board/juno/juno_bl1_setup.c \ 81 drivers/arm/sp805/sp805.c \ 82 ${JUNO_INTERCONNECT_SOURCES} \ 83 ${JUNO_SECURITY_SOURCES} 84 85BL2_SOURCES += drivers/arm/sp805/sp805.c \ 86 lib/utils/mem_region.c \ 87 plat/arm/board/juno/juno_err.c \ 88 plat/arm/board/juno/juno_bl2_setup.c \ 89 plat/arm/common/arm_nor_psci_mem_protect.c \ 90 ${JUNO_SECURITY_SOURCES} 91 92BL2U_SOURCES += ${JUNO_SECURITY_SOURCES} 93 94BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ 95 lib/cpus/aarch64/cortex_a53.S \ 96 lib/cpus/aarch64/cortex_a57.S \ 97 lib/cpus/aarch64/cortex_a72.S \ 98 lib/utils/mem_region.c \ 99 lib/fconf/fconf.c \ 100 lib/fconf/fconf_dyn_cfg_getter.c \ 101 plat/arm/board/juno/juno_bl31_setup.c \ 102 plat/arm/board/juno/juno_pm.c \ 103 plat/arm/board/juno/juno_topology.c \ 104 plat/arm/common/arm_nor_psci_mem_protect.c \ 105 ${JUNO_INTERCONNECT_SOURCES} \ 106 ${JUNO_SECURITY_SOURCES} 107 108BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 109 110ifeq (${CSS_USE_SCMI_SDS_DRIVER},1) 111BL1_SOURCES += drivers/arm/css/sds/sds.c 112endif 113 114ifeq (${TRUSTED_BOARD_BOOT}, 1) 115 # Enable Juno specific TBBR images 116 $(eval $(call add_define,PLAT_TBBR_IMG_DEF)) 117 DTC_CPPFLAGS += ${PLAT_INCLUDES} 118 119 BL1_SOURCES += plat/arm/board/juno/juno_trusted_boot.c 120 BL2_SOURCES += plat/arm/board/juno/juno_trusted_boot.c 121 122 ifeq (${COT_DESC_IN_DTB},0) 123 BL2_SOURCES += plat/arm/board/juno/juno_tbbr_cot_bl2.c 124 endif 125endif 126 127ifeq (${MEASURED_BOOT},1) 128MBEDTLS_CONFIG_FILE ?= "<plat_juno_mbedtls_config.h>" 129MBOOT_TPM_HASH_ALG ?= ${HASH_ALG} 130 131PLAT_INCLUDES += -Iinclude/lib/psa 132 133BL1_SOURCES += plat/arm/board/juno/juno_common_measured_boot.c \ 134 plat/arm/board/juno/juno_bl1_measured_boot.c \ 135 common/measured_boot_helpers.c 136 137BL2_SOURCES += plat/arm/board/juno/juno_common_measured_boot.c \ 138 plat/arm/board/juno/juno_bl2_measured_boot.c \ 139 common/measured_boot_helpers.c 140endif 141 142endif 143 144ifneq (${RESET_TO_BL31},0) 145 $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \ 146 Please set RESET_TO_BL31 to 0.") 147endif 148 149ifeq ($(USE_ROMLIB),1) 150all: $(BUILD_PLAT)/bl1_romlib.bin 151endif 152 153$(BUILD_PLAT)/bl1_romlib.bin: $(BUILD_PLAT)/bl1.bin $(BUILD_PLAT)/romlib/romlib.bin 154 $(s)echo "Building combined BL1 and ROMLIB binary for Juno $@" 155 ./lib/romlib/gen_combined_bl1_romlib.sh -o bl1_romlib.bin $(BUILD_PLAT) 156 157# Errata workarounds for Cortex-A53: 158ERRATA_A53_819472 := 1 159ERRATA_A53_824069 := 1 160ERRATA_A53_826319 := 1 161ERRATA_A53_827319 := 1 162ERRATA_A53_835769 := 1 163ERRATA_A53_836870 := 1 164ERRATA_A53_843419 := 1 165ERRATA_A53_855873 := 1 166 167# Errata workarounds for Cortex-A57: 168ERRATA_A57_806969 := 0 169ERRATA_A57_813419 := 1 170ERRATA_A57_813420 := 1 171ERRATA_A57_814670 := 1 172ERRATA_A57_817169 := 1 173ERRATA_A57_826974 := 1 174ERRATA_A57_826977 := 1 175ERRATA_A57_828024 := 1 176ERRATA_A57_829520 := 1 177ERRATA_A57_833471 := 1 178ERRATA_A57_859972 := 0 179 180# Errata workarounds for Cortex-A72: 181ERRATA_A72_859971 := 0 182 183# Enable option to skip L1 data cache flush during the Cortex-A57 cluster 184# power down sequence 185SKIP_A57_L1_FLUSH_PWR_DWN := 1 186 187# Do not enable SVE 188ENABLE_SVE_FOR_NS := 0 189 190# Enable the dynamic translation tables library. 191ifeq (${ARCH},aarch32) 192 ifeq (${RESET_TO_SP_MIN},1) 193 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 194 endif 195else 196 ifeq (${RESET_TO_BL31},1) 197 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 198 endif 199endif 200 201ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 202 ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 203 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 204 else 205 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 206 endif 207endif 208 209BL1_CPPFLAGS += -march=armv8-a+crc 210BL2_CPPFLAGS += -march=armv8-a+crc 211BL2U_CPPFLAGS += -march=armv8-a+crc 212BL31_CPPFLAGS += -march=armv8-a+crc 213BL32_CPPFLAGS += -march=armv8-a+crc 214 215# Add the FDT_SOURCES and options for Dynamic Config 216FDT_SOURCES += plat/arm/board/juno/fdts/${PLAT}_fw_config.dts \ 217 plat/arm/board/juno/fdts/${PLAT}_tb_fw_config.dts \ 218 fdts/${PLAT}.dts 219 220FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 221TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 222HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb 223 224# Add the FW_CONFIG to FIP and specify the same to certtool 225$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 226# Add the TB_FW_CONFIG to FIP and specify the same to certtool 227$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 228# Add the HW_CONFIG to FIP and specify the same to certtool 229$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG})) 230 231 232ifeq (${SPD},spmd) 233ifneq ($(ARM_SPMC_MANIFEST_DTS),) 234FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 235endif 236endif 237 238include drivers/arm/ethosn/ethosn_npu.mk 239include plat/arm/board/common/board_common.mk 240include plat/arm/common/arm_common.mk 241include plat/arm/soc/common/soc_css.mk 242include plat/arm/css/common/css_common.mk 243