1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_nano.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Nano must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Nano supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "Arm C1-Nano needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue c1_nano 30 31workaround_reset_start c1_nano, ERRATUM(3392149), ERRATA_C1NANO_3392149 32 sysreg_bit_set C1_NANO_IMP_CPUACTLR3_EL1, BIT(39) 33workaround_reset_end c1_nano, ERRATUM(3392149) 34 35check_erratum_ls c1_nano, ERRATUM(3392149), CPU_REV(0, 0) 36 37workaround_reset_start c1_nano, ERRATUM(3419531), ERRATA_C1NANO_3419531 38 sysreg_bit_set C1_NANO_IMP_CPUACTLR_EL1, BIT(27) 39workaround_reset_end c1_nano, ERRATUM(3419531) 40 41check_erratum_ls c1_nano, ERRATUM(3419531), CPU_REV(0, 0) 42 43workaround_reset_start c1_nano, ERRATUM(3437202), ERRATA_C1NANO_3437202 44 sysreg_bit_set C1_NANO_IMP_CPUACTLR_EL1, BIT(26) 45workaround_reset_end c1_nano, ERRATUM(3437202) 46 47check_erratum_ls c1_nano, ERRATUM(3437202), CPU_REV(0, 0) 48 49workaround_reset_start c1_nano, ERRATUM(3516455), ERRATA_C1NANO_3516455 50#if ENABLE_SME_FOR_NS 51#if ENABLE_SME_FOR_NS == 2 52 is_feat_sme_present_asm x1 53 beq 1f 54#endif 55 56 mov x0, #0 57 msr C1_NANO_IMP_CPUPSELR_EL3, x0 58 isb 59 ldr x0, =0xA0008000 60 msr C1_NANO_IMP_CPUPOR_EL3, x0 61 ldr x0, =0xFE808000 62 msr C1_NANO_IMP_CPUPMR_EL3, x0 63 ldr x0, =0x7F9 64 movk x0, #0x20, LSL #32 65 msr C1_NANO_IMP_CPUPCR_EL3, x0 66 isb 67 mov x0, #1 68 msr C1_NANO_IMP_CPUPSELR_EL3, x0 69 isb 70 ldr x0, =0xA4604000 71 msr C1_NANO_IMP_CPUPOR_EL3, x0 72 ldr x0, =0xBE604000 73 msr C1_NANO_IMP_CPUPMR_EL3, x0 74 ldr x0, =0x7F9 75 movk x0, #0x20, LSL #32 76 msr C1_NANO_IMP_CPUPCR_EL3, x0 77 78 1: 79#endif 80workaround_reset_end c1_nano, ERRATUM(3516455) 81 82check_erratum_ls c1_nano, ERRATUM(3516455), CPU_REV(0, 0) 83 84workaround_reset_start c1_nano, ERRATUM(3616450), ERRATA_C1NANO_3616450 85#if ENABLE_SME_FOR_NS 86#if ENABLE_SME_FOR_NS == 2 87 is_feat_sme_present_asm x1 88 beq 1f 89#endif 90 91 sysreg_bit_set C1_NANO_IMP_CPUACTLR_EL1, BIT(29) 92 93 1: 94#endif 95workaround_reset_end c1_nano, ERRATUM(3616450) 96 97check_erratum_ls c1_nano, ERRATUM(3616450), CPU_REV(0, 0) 98 99workaround_reset_start c1_nano, ERRATUM(3630925), ERRATA_C1NANO_3630925 100 sysreg_bitfield_insert C1_NANO_IMP_CPUPWRCTLR_EL1, \ 101 C1_NANO_IMP_CPUPWRCTLR_EL1_WFE_RET_CTRL_BIT, \ 102 C1_NANO_IMP_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT, \ 103 C1_NANO_IMP_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH 104 105 sysreg_bitfield_insert C1_NANO_IMP_CPUPWRCTLR_EL1, \ 106 C1_NANO_IMP_CPUPWRCTLR_EL1_WFI_RET_CTRL_BIT, \ 107 C1_NANO_IMP_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT, \ 108 C1_NANO_IMP_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH 109workaround_reset_end c1_nano, ERRATUM(3630925) 110 111check_erratum_ls c1_nano, ERRATUM(3630925), CPU_REV(0, 0) 112 113cpu_reset_func_start c1_nano 114 /* ---------------------------------------------------- 115 * Disable speculative loads 116 * ---------------------------------------------------- 117 */ 118 msr SSBS, xzr 119 /* model bug: not cleared on reset */ 120 sysreg_bit_clear C1_NANO_IMP_CPUPWRCTLR_EL1, \ 121 C1_NANO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 122 enable_mpmm 123cpu_reset_func_end c1_nano 124 125func c1_nano_core_pwr_dwn 126 /* --------------------------------------------------- 127 * Enable CPU power down bit in power control register 128 * --------------------------------------------------- 129 */ 130 sysreg_bit_toggle C1_NANO_IMP_CPUPWRCTLR_EL1, \ 131 C1_NANO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 132 isb 133 apply_erratum c1_nano, ERRATUM(3754876), ERRATA_C1NANO_3754876 134 signal_pabandon_handled 135 ret 136endfunc c1_nano_core_pwr_dwn 137 138.section .rodata.c1_nano_regs, "aS" 139c1_nano_regs: /* The ASCII list of register names to be reported */ 140 .asciz "cpuectlr_el1", "" 141 142func c1_nano_cpu_reg_dump 143 adr x6, c1_nano_regs 144 mrs x8, C1_NANO_IMP_CPUECTLR_EL1 145 ret 146endfunc c1_nano_cpu_reg_dump 147 148declare_cpu_ops c1_nano, C1_NANO_MIDR, \ 149 c1_nano_reset_func, \ 150 c1_nano_core_pwr_dwn 151