1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x925.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-X925 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-X925 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue cortex_x925 26 27workaround_reset_start cortex_x925, ERRATUM(2900952), ERRATA_DSU_2900952 28 errata_dsu_2900952_wa_apply 29workaround_reset_end cortex_x925, ERRATUM(2900952) 30 31check_erratum_custom_start cortex_x925, ERRATUM(2900952) 32 check_errata_dsu_2900952_applies 33 ret 34check_erratum_custom_end cortex_x925, ERRATUM(2900952) 35 36add_erratum_entry cortex_x925, ERRATUM(3701747), ERRATA_X925_3701747 37 38.global check_erratum_cortex_x925_3701747 39check_erratum_ls cortex_x925, ERRATUM(3701747), CPU_REV(0, 1) 40 41workaround_reset_start cortex_x925, ERRATUM(2921199), ERRATA_X925_2921199 42 sysreg_bit_set CORTEX_X925_CPUACTLR5_EL1, BIT(14) 43workaround_reset_end cortex_x925, ERRATUM(2921199) 44 45check_erratum_ls cortex_x925, ERRATUM(2921199), CPU_REV(0, 0) 46 47workaround_reset_start cortex_x925, ERRATUM(2963999), ERRATA_X925_2963999 48 /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ 49 ldr x0, =0x0 50 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ 51 ldr x0, =0xd5380000 52 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ 53 ldr x0, =0xFFFFFF40 54 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ 55 ldr x0, =0x000080010033f 56 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ 57 isb 58workaround_reset_end cortex_x925, ERRATUM(2963999) 59 60check_erratum_ls cortex_x925, ERRATUM(2963999), CPU_REV(0, 0) 61 62/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 63workaround_reset_start cortex_x925, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 64 sysreg_bit_set CORTEX_X925_CPUECTLR_EL1, BIT(46) 65workaround_reset_end cortex_x925, CVE(2024, 5660) 66 67check_erratum_ls cortex_x925, CVE(2024, 5660), CPU_REV(0, 1) 68 69 /* ---------------------------------------------------------------- 70 * CVE-2024-7881 is mitigated for Cortex-X925 using erratum 3692980 71 * workaround by disabling the affected prefetcher setting 72 * CPUACTLR6_EL1[41]. 73 * ---------------------------------------------------------------- 74 */ 75workaround_reset_start cortex_x925, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 76 sysreg_bit_set CORTEX_X925_CPUACTLR6_EL1, BIT(41) 77workaround_reset_end cortex_x925, CVE(2024, 7881) 78 79check_erratum_ls cortex_x925, CVE(2024, 7881), CPU_REV(0, 1) 80 81cpu_reset_func_start cortex_x925 82 /* Disable speculative loads */ 83 msr SSBS, xzr 84 enable_mpmm 85cpu_reset_func_end cortex_x925 86 87 /* ---------------------------------------------------- 88 * HW will do the cache maintenance while powering down 89 * ---------------------------------------------------- 90 */ 91func cortex_x925_core_pwr_dwn 92 /* --------------------------------------------------- 93 * Enable CPU power down bit in power control register 94 * --------------------------------------------------- 95 */ 96 sysreg_bit_set CORTEX_X925_CPUPWRCTLR_EL1, CORTEX_X925_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 97 isb 98 ret 99endfunc cortex_x925_core_pwr_dwn 100 101 /* --------------------------------------------- 102 * This function provides Cortex-X925 specific 103 * register information for crash reporting. 104 * It needs to return with x6 pointing to 105 * a list of register names in ascii and 106 * x8 - x15 having values of registers to be 107 * reported. 108 * --------------------------------------------- 109 */ 110.section .rodata.cortex_x925_regs, "aS" 111cortex_x925_regs: /* The ascii list of register names to be reported */ 112 .asciz "cpuectlr_el1", "" 113 114func cortex_x925_cpu_reg_dump 115 adr x6, cortex_x925_regs 116 mrs x8, CORTEX_X925_CPUECTLR_EL1 117 ret 118endfunc cortex_x925_cpu_reg_dump 119 120declare_cpu_ops cortex_x925, CORTEX_X925_MIDR, \ 121 cortex_x925_reset_func, \ 122 cortex_x925_core_pwr_dwn 123