| 55df84f9 | 15-Nov-2018 |
Igal Liberman <igall@marvell.com> |
mvebu: cp110: avoid pcie power on/off sequence when called from Linux
In Armada 8K DB boards, PCIe initialization can be executed only once
because PCIe reset performed during chip power on and it c
mvebu: cp110: avoid pcie power on/off sequence when called from Linux
In Armada 8K DB boards, PCIe initialization can be executed only once
because PCIe reset performed during chip power on and it cannot be
executed via GPIO later.
This means that power on can be executed only once, when it's called
from the bootloader.
Power on:
Read bit 21 of the mode, it marks if the caller is
the bootloader or the Linux Kernel.
Power off:
Check if the comphy was already configured to PCIe, if yes,
check if the caller is bootloader, if both conditions are true
(PCIe mode and called by Linux) - skip the power-off.
In addition, fix incorrect documentation describing mode fields -
PCIe width is 3 bits, not 2.
NOTE: with this patch, please use LK4.14.76 (LK4.4.120 may not work
with it).
Change-Id: I4b929011f97a0a1869a51ba378687e78b3eca4ff
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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| 7e4d5620 | 21-Jul-2018 |
Icenowy Zheng <icenowy@aosc.io> |
drivers: mentor: extract MI2CV driver from Marvell driver
The Marvell A8K SoCs use the MI2CV IP core from Mentor Graphics, which
is also used by Allwinner.
As Mentor Graphics allows a lot of custom
drivers: mentor: extract MI2CV driver from Marvell driver
The Marvell A8K SoCs use the MI2CV IP core from Mentor Graphics, which
is also used by Allwinner.
As Mentor Graphics allows a lot of customization, the MI2CV in the two
SoC families are not compatible, and driver modifications are needed.
Extract the common code to a MI2CV driver.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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| 3c0024cc | 16-Jul-2018 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
mvebu: cp110: fix spelling in register definition
Use PF instead of PP post-fix, since it is referring to "Phase Final"
(only G3 related register had correct spelling for relevant bit).
Change-Id:
mvebu: cp110: fix spelling in register definition
Use PF instead of PP post-fix, since it is referring to "Phase Final"
(only G3 related register had correct spelling for relevant bit).
Change-Id: Ia5a9c9c78b74b15f7f8adde2c3ef4784c513da2c
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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| 3a9f8eec | 13-Jun-2018 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
drivers: marvell: mc_trustzone: add driver for mc trustzone
Add simple driver which allows to configure the memory controller trust
zones. It is responsible for opening mc trustzone window, with
app
drivers: marvell: mc_trustzone: add driver for mc trustzone
Add simple driver which allows to configure the memory controller trust
zones. It is responsible for opening mc trustzone window, with
appropriate base address, size and attributes.
Example of usage in upcoming commits.
Change-Id: I8bea17754d31451b305040ee7de331fb8db0c63f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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| d5a6f86c | 26-Feb-2018 |
Konstantin Porotchkin <kostap@marvell.com> |
marvell: drivers: Add thermal driver
Add thermal driver for A8K SoC family.
The termal unit data is used by Marvell DRAM initialization
code for optimizing the memory controller configuration
Chang
marvell: drivers: Add thermal driver
Add thermal driver for A8K SoC family.
The termal unit data is used by Marvell DRAM initialization
code for optimizing the memory controller configuration
Change-Id: Iad92689fa6e4224a89d872e9aa015393abd9cf73
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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| 152b0e47 | 26-Feb-2018 |
Konstantin Porotchkin <kostap@marvell.com> |
marvell: drivers: Add L3/system cache management drivers
Add LLC (L3) cache management drivers for Marvell SoCs
AP806, AP807 and AP810
Change-Id: Ic70710f9bc5b6b48395d62212df7011e2fbb5894
Signed-of
marvell: drivers: Add L3/system cache management drivers
Add LLC (L3) cache management drivers for Marvell SoCs
AP806, AP807 and AP810
Change-Id: Ic70710f9bc5b6b48395d62212df7011e2fbb5894
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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| 031542fc | 26-Feb-2018 |
Konstantin Porotchkin <kostap@marvell.com> |
marvell: drivers: Add MoChi drivers
Add ModularChip and MCI drivers for A8K SoC family.
ModularChip drivers include support for the internal building
blocks of Marvell ARMADA SoCs - APN806, APN807 a
marvell: drivers: Add MoChi drivers
Add ModularChip and MCI drivers for A8K SoC family.
ModularChip drivers include support for the internal building
blocks of Marvell ARMADA SoCs - APN806, APN807 and CP110
Change-Id: I9559343788fa2e5eb47e6384a4a7d47408787c02
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
show more ...
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