1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <debug.h> 10 #include <gicv3.h> 11 #include <mmio.h> 12 #include <plat_imx8.h> 13 #include <psci.h> 14 #include <sci/sci.h> 15 #include <stdbool.h> 16 17 const static int ap_core_index[PLATFORM_CORE_COUNT] = { 18 SC_R_A35_0, SC_R_A35_1, SC_R_A35_2, SC_R_A35_3 19 }; 20 21 int imx_pwr_domain_on(u_register_t mpidr) 22 { 23 int ret = PSCI_E_SUCCESS; 24 unsigned int cpu_id; 25 26 cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 27 28 printf("imx_pwr_domain_on cpu_id %d\n", cpu_id); 29 30 if (sc_pm_set_resource_power_mode(ipc_handle, ap_core_index[cpu_id], 31 SC_PM_PW_MODE_ON) != SC_ERR_NONE) { 32 ERROR("core %d power on failed!\n", cpu_id); 33 ret = PSCI_E_INTERN_FAIL; 34 } 35 36 if (sc_pm_cpu_start(ipc_handle, ap_core_index[cpu_id], 37 true, BL31_BASE) != SC_ERR_NONE) { 38 ERROR("boot core %d failed!\n", cpu_id); 39 ret = PSCI_E_INTERN_FAIL; 40 } 41 42 return ret; 43 } 44 45 void imx_pwr_domain_on_finish(const psci_power_state_t *target_state) 46 { 47 plat_gic_pcpu_init(); 48 plat_gic_cpuif_enable(); 49 } 50 51 int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint) 52 { 53 return PSCI_E_SUCCESS; 54 } 55 56 void imx_pwr_domain_off(const psci_power_state_t *target_state) 57 { 58 u_register_t mpidr = read_mpidr_el1(); 59 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 60 61 plat_gic_cpuif_disable(); 62 sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id], 63 SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_NONE); 64 printf("turn off core:%d\n", cpu_id); 65 } 66 67 void imx_domain_suspend(const psci_power_state_t *target_state) 68 { 69 u_register_t mpidr = read_mpidr_el1(); 70 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 71 72 plat_gic_cpuif_disable(); 73 74 sc_pm_set_cpu_resume_addr(ipc_handle, ap_core_index[cpu_id], BL31_BASE); 75 sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id], 76 SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_GIC); 77 } 78 79 void imx_domain_suspend_finish(const psci_power_state_t *target_state) 80 { 81 u_register_t mpidr = read_mpidr_el1(); 82 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 83 84 sc_pm_req_low_power_mode(ipc_handle, ap_core_index[cpu_id], 85 SC_PM_PW_MODE_ON); 86 87 plat_gic_cpuif_enable(); 88 } 89 90 static const plat_psci_ops_t imx_plat_psci_ops = { 91 .pwr_domain_on = imx_pwr_domain_on, 92 .pwr_domain_on_finish = imx_pwr_domain_on_finish, 93 .validate_ns_entrypoint = imx_validate_ns_entrypoint, 94 .system_off = imx_system_off, 95 .system_reset = imx_system_reset, 96 .pwr_domain_off = imx_pwr_domain_off, 97 .pwr_domain_suspend = imx_domain_suspend, 98 .pwr_domain_suspend_finish = imx_domain_suspend_finish, 99 .get_sys_suspend_power_state = imx_get_sys_suspend_power_state, 100 .validate_power_state = imx_validate_power_state, 101 }; 102 103 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 104 const plat_psci_ops_t **psci_ops) 105 { 106 imx_mailbox_init(sec_entrypoint); 107 *psci_ops = &imx_plat_psci_ops; 108 109 /* Request low power mode for A35 cluster, only need to do once */ 110 sc_pm_req_low_power_mode(ipc_handle, SC_R_A35, SC_PM_PW_MODE_OFF); 111 112 /* Request RUN and LP modes for DDR, system interconnect etc. */ 113 sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, 114 SC_PM_SYS_IF_DDR, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY); 115 sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, 116 SC_PM_SYS_IF_MU, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY); 117 sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, 118 SC_PM_SYS_IF_INTERCONNECT, SC_PM_PW_MODE_ON, 119 SC_PM_PW_MODE_STBY); 120 121 return 0; 122 } 123