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Searched refs:reg_ctx (Results 1 – 21 of 21) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkdec/h265d/
H A Dhal_h265d_vdpu382.c100 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu382_init() local
102 mpp_slots_set_prop(reg_ctx->slots, SLOTS_HOR_ALIGN, hevc_hor_align); in hal_h265d_vdpu382_init()
103 mpp_slots_set_prop(reg_ctx->slots, SLOTS_VER_ALIGN, hevc_ver_align); in hal_h265d_vdpu382_init()
105 reg_ctx->scaling_qm = mpp_calloc(DXVA_Qmatrix_HEVC, 1); in hal_h265d_vdpu382_init()
106 if (reg_ctx->scaling_qm == NULL) { in hal_h265d_vdpu382_init()
111 reg_ctx->scaling_rk = mpp_calloc(scalingFactor_t, 1); in hal_h265d_vdpu382_init()
112 reg_ctx->pps_buf = mpp_calloc(RK_U64, 15); in hal_h265d_vdpu382_init()
113 reg_ctx->sw_rps_buf = mpp_calloc(RK_U64, 400); in hal_h265d_vdpu382_init()
115 if (reg_ctx->scaling_rk == NULL) { in hal_h265d_vdpu382_init()
120 if (reg_ctx->group == NULL) { in hal_h265d_vdpu382_init()
[all …]
H A Dhal_h265d_vdpu34x.c102 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu34x_init() local
104 mpp_slots_set_prop(reg_ctx->slots, SLOTS_HOR_ALIGN, hevc_hor_align); in hal_h265d_vdpu34x_init()
105 mpp_slots_set_prop(reg_ctx->slots, SLOTS_VER_ALIGN, hevc_ver_align); in hal_h265d_vdpu34x_init()
107 reg_ctx->scaling_qm = mpp_calloc(DXVA_Qmatrix_HEVC, 1); in hal_h265d_vdpu34x_init()
108 if (reg_ctx->scaling_qm == NULL) { in hal_h265d_vdpu34x_init()
113 reg_ctx->scaling_rk = mpp_calloc(scalingFactor_t, 1); in hal_h265d_vdpu34x_init()
114 reg_ctx->pps_buf = mpp_calloc(RK_U64, 15); in hal_h265d_vdpu34x_init()
115 reg_ctx->sw_rps_buf = mpp_calloc(RK_U64, 400); in hal_h265d_vdpu34x_init()
117 if (reg_ctx->scaling_rk == NULL) { in hal_h265d_vdpu34x_init()
122 if (reg_ctx->group == NULL) { in hal_h265d_vdpu34x_init()
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H A Dhal_h265d_vdpu383.c112 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu383_init() local
114 mpp_slots_set_prop(reg_ctx->slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64); in hal_h265d_vdpu383_init()
115 mpp_slots_set_prop(reg_ctx->slots, SLOTS_VER_ALIGN, hevc_ver_align); in hal_h265d_vdpu383_init()
117 reg_ctx->scaling_qm = mpp_calloc(DXVA_Qmatrix_HEVC, 1); in hal_h265d_vdpu383_init()
118 if (reg_ctx->scaling_qm == NULL) { in hal_h265d_vdpu383_init()
123 reg_ctx->scaling_rk = mpp_calloc(scalingFactor_t, 1); in hal_h265d_vdpu383_init()
124 reg_ctx->pps_buf = mpp_calloc(RK_U64, 24); in hal_h265d_vdpu383_init()
125 reg_ctx->sw_rps_buf = mpp_calloc(RK_U64, 400); in hal_h265d_vdpu383_init()
127 if (reg_ctx->scaling_rk == NULL) { in hal_h265d_vdpu383_init()
132 if (reg_ctx->group == NULL) { in hal_h265d_vdpu383_init()
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H A Dhal_h265d_rkv.c45 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_alloc_res() local
46 if (reg_ctx->fast_mode) { in hal_h265d_alloc_res()
48 reg_ctx->g_buf[i].hw_regs = in hal_h265d_alloc_res()
50 ret = mpp_buffer_get(reg_ctx->group, in hal_h265d_alloc_res()
51 &reg_ctx->g_buf[i].scaling_list_data, in hal_h265d_alloc_res()
58 ret = mpp_buffer_get(reg_ctx->group, &reg_ctx->g_buf[i].pps_data, in hal_h265d_alloc_res()
65 ret = mpp_buffer_get(reg_ctx->group, &reg_ctx->g_buf[i].rps_data, in hal_h265d_alloc_res()
73 reg_ctx->hw_regs = mpp_calloc_size(void, sizeof(H265d_REGS_t)); in hal_h265d_alloc_res()
74 ret = mpp_buffer_get(reg_ctx->group, &reg_ctx->scaling_list_data, in hal_h265d_alloc_res()
81 ret = mpp_buffer_get(reg_ctx->group, &reg_ctx->pps_data, PPS_SIZE); in hal_h265d_alloc_res()
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H A Dhal_h265d_vdpu384a.c91 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu384a_init() local
93 mpp_slots_set_prop(reg_ctx->slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64); in hal_h265d_vdpu384a_init()
94 mpp_slots_set_prop(reg_ctx->slots, SLOTS_VER_ALIGN, hevc_ver_align); in hal_h265d_vdpu384a_init()
96 reg_ctx->scaling_qm = mpp_calloc(DXVA_Qmatrix_HEVC, 1); in hal_h265d_vdpu384a_init()
97 if (reg_ctx->scaling_qm == NULL) { in hal_h265d_vdpu384a_init()
102 reg_ctx->scaling_rk = mpp_calloc(scalingFactor_t, 1); in hal_h265d_vdpu384a_init()
103 reg_ctx->pps_buf = mpp_calloc(RK_U8, SPSPPS_ALIGNED_SIZE); in hal_h265d_vdpu384a_init()
105 if (reg_ctx->scaling_rk == NULL) { in hal_h265d_vdpu384a_init()
110 if (reg_ctx->group == NULL) { in hal_h265d_vdpu384a_init()
111 ret = mpp_buffer_group_get_internal(&reg_ctx->group, MPP_BUFFER_TYPE_ION); in hal_h265d_vdpu384a_init()
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H A Dhal_h265d_com.c699 HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal; in hal_h265d_output_scalinglist_packet() local
703 if (memcmp((void*)&dxva_cxt->qm, reg_ctx->scaling_qm, sizeof(DXVA_Qmatrix_HEVC))) { in hal_h265d_output_scalinglist_packet()
724 hal_record_scaling_list((scalingFactor_t *)reg_ctx->scaling_rk, &sl); in hal_h265d_output_scalinglist_packet()
726 memcpy(ptr, reg_ctx->scaling_rk, sizeof(scalingFactor_t)); in hal_h265d_output_scalinglist_packet()
/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_rkv_reg.c312 H264dRkvRegCtx_t *reg_ctx = (H264dRkvRegCtx_t *)p_hal->reg_ctx; in prepare_spspps() local
331 mpp_put_bits(&bp, mpp_buffer_get_fd(reg_ctx->sclst_buf), 32); in prepare_spspps()
528 H264dRkvRegCtx_t *reg_ctx = (H264dRkvRegCtx_t *)p_hal->reg_ctx; in set_registers() local
531 p_regs->sw06.cabactbl_base = mpp_buffer_get_fd(reg_ctx->cabac_buf); in set_registers()
550 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(H264dRkvRegCtx_t))); in rkv_h264d_init()
551 H264dRkvRegCtx_t *reg_ctx = (H264dRkvRegCtx_t *)p_hal->reg_ctx; in rkv_h264d_init() local
554 &reg_ctx->cabac_buf, RKV_CABAC_TAB_SIZE)); in rkv_h264d_init()
556 &reg_ctx->errinfo_buf, RKV_ERROR_INFO_SIZE)); in rkv_h264d_init()
559 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1; in rkv_h264d_init()
561 reg_ctx->reg_buf[i].regs = mpp_calloc(H264dRkvRegs_t, 1); in rkv_h264d_init()
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H A Dhal_h264d_vdpu1.c423 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in vdpu1_set_vlc_regs() local
424 RK_U32 *pocBase = (RK_U32 *)reg_ctx->poc_ptr; in vdpu1_set_vlc_regs()
651 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in vdpu1_set_asic_regs() local
654 RK_U32 *ptr = (RK_U32 *)reg_ctx->sclst_ptr; in vdpu1_set_asic_regs()
676 p_regs->SwReg40.qtable_st_adr = mpp_buffer_get_fd(reg_ctx->buf); in vdpu1_set_asic_regs()
752 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(H264dVdpuRegCtx_t))); in vdpu1_h264d_init()
753 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in vdpu1_h264d_init() local
757 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1; in vdpu1_h264d_init()
761 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, &reg_ctx->reg_buf[i].buf, buf_size)); in vdpu1_h264d_init()
762 reg_ctx->reg_buf[i].cabac_ptr = mpp_buffer_get_ptr(reg_ctx->reg_buf[i].buf); in vdpu1_h264d_init()
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H A Dhal_h264d_vdpu2.c459 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in set_vlc_regs() local
460 RK_U32 *ptr = (RK_U32 *)reg_ctx->poc_ptr; in set_vlc_regs()
483 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in set_vlc_regs() local
484 RK_U32 *ptr_tmp = (RK_U32 *)reg_ctx->poc_ptr; in set_vlc_regs()
760 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in set_asic_regs() local
763 RK_U32 *ptr = (RK_U32 *)reg_ctx->sclst_ptr; in set_asic_regs()
784 p_regs->sw61.qtable_st_adr = mpp_buffer_get_fd(reg_ctx->buf); in set_asic_regs()
809 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(H264dVdpuRegCtx_t))); in vdpu2_h264d_init()
810 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in vdpu2_h264d_init() local
814 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1; in vdpu2_h264d_init()
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H A Dhal_h264d_vdpu383.c132 Vdpu383H264dRegCtx *ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx; in vdpu383_setup_scale_origin_bufs()
420 Vdpu383H264dRegCtx *ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx; in set_registers()
532 Vdpu383H264dRegCtx *reg_ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx; in set_registers() local
547 regs->common_addr.reg130_cabactbl_base = reg_ctx->bufs_fd; in set_registers()
548 mpp_dev_set_reg_offset(p_hal->dev, 130, reg_ctx->offset_cabac); in set_registers()
637 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Vdpu383H264dRegCtx))); in vdpu383_h264d_init()
638 Vdpu383H264dRegCtx *reg_ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx; in vdpu383_h264d_init() local
643 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, &reg_ctx->bufs, in vdpu383_h264d_init()
645 reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs); in vdpu383_h264d_init()
646 reg_ctx->bufs_ptr = mpp_buffer_get_ptr(reg_ctx->bufs); in vdpu383_h264d_init()
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H A Dhal_h264d_vdpu34x.c653 Vdpu34xH264dRegCtx *reg_ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx; in set_registers() local
659 regs->h264d_addr.cabactbl_base = reg_ctx->bufs_fd; in set_registers()
660 mpp_dev_set_reg_offset(p_hal->dev, 197, reg_ctx->offset_cabac); in set_registers()
715 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Vdpu34xH264dRegCtx))); in vdpu34x_h264d_init()
716 Vdpu34xH264dRegCtx *reg_ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx; in vdpu34x_h264d_init() local
721 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, &reg_ctx->bufs, in vdpu34x_h264d_init()
723 reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs); in vdpu34x_h264d_init()
724 reg_ctx->bufs_ptr = mpp_buffer_get_ptr(reg_ctx->bufs); in vdpu34x_h264d_init()
725 reg_ctx->offset_cabac = VDPU34X_CABAC_TAB_OFFSET; in vdpu34x_h264d_init()
726 reg_ctx->offset_errinfo = VDPU34X_ERROR_INFO_OFFSET; in vdpu34x_h264d_init()
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H A Dhal_h264d_vdpu382.c540 Vdpu382H264dRegCtx *ctx = (Vdpu382H264dRegCtx *)p_hal->reg_ctx; in set_registers()
667 Vdpu382H264dRegCtx *reg_ctx = (Vdpu382H264dRegCtx *)p_hal->reg_ctx; in set_registers() local
673 regs->h264d_addr.cabactbl_base = reg_ctx->bufs_fd; in set_registers()
674 mpp_dev_set_reg_offset(p_hal->dev, 197, reg_ctx->offset_cabac); in set_registers()
736 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Vdpu382H264dRegCtx))); in vdpu382_h264d_init()
737 Vdpu382H264dRegCtx *reg_ctx = (Vdpu382H264dRegCtx *)p_hal->reg_ctx; in vdpu382_h264d_init() local
742 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, &reg_ctx->bufs, in vdpu382_h264d_init()
744 reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs); in vdpu382_h264d_init()
745 reg_ctx->bufs_ptr = mpp_buffer_get_ptr(reg_ctx->bufs); in vdpu382_h264d_init()
746 reg_ctx->offset_cabac = VDPU382_CABAC_TAB_OFFSET; in vdpu382_h264d_init()
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H A Dhal_h264d_vdpu384a.c119 Vdpu384aH264dRegCtx *ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx; in vdpu384a_setup_scale_origin_bufs()
356 Vdpu384aH264dRegCtx *ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx; in set_registers()
595 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Vdpu384aH264dRegCtx))); in vdpu384a_h264d_init()
596 Vdpu384aH264dRegCtx *reg_ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx; in vdpu384a_h264d_init() local
601 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, &reg_ctx->bufs, in vdpu384a_h264d_init()
603 reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs); in vdpu384a_h264d_init()
604 reg_ctx->bufs_ptr = mpp_buffer_get_ptr(reg_ctx->bufs); in vdpu384a_h264d_init()
605 reg_ctx->offset_errinfo = VDPU384A_ERROR_INFO_OFFSET; in vdpu384a_h264d_init()
607 reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu384aH264dRegSet, 1); in vdpu384a_h264d_init()
608 init_ctrl_regs(reg_ctx->reg_buf[i].regs); in vdpu384a_h264d_init()
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H A Dhal_h264d_global.h118 void *reg_ctx; member
/rockchip-linux_mpp/mpp/hal/rkdec/avs2d/
H A Dhal_avs2d_vdpu383.c324 Avs2dRkvRegCtx_t *reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx; in hal_avs2d_rcb_info_update() local
328 RK_S32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1; in hal_avs2d_rcb_info_update()
332 reg_ctx->rcb_buf_size = vdpu383_get_rcb_buf_size(reg_ctx->rcb_info, width, height); in hal_avs2d_rcb_info_update()
333 avs2d_refine_rcb_size(reg_ctx->rcb_info, width, height, (void *)&p_hal->syntax); in hal_avs2d_rcb_info_update()
338 if (reg_ctx->rcb_buf[i]) { in hal_avs2d_rcb_info_update()
339 mpp_buffer_put(reg_ctx->rcb_buf[i]); in hal_avs2d_rcb_info_update()
340 reg_ctx->rcb_buf[i] = NULL; in hal_avs2d_rcb_info_update()
343 ret = mpp_buffer_get(p_hal->buf_group, &rcb_buf, reg_ctx->rcb_buf_size); in hal_avs2d_rcb_info_update()
347 reg_ctx->rcb_buf[i] = rcb_buf; in hal_avs2d_rcb_info_update()
502 Avs2dRkvRegCtx_t *reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx; in hal_avs2d_vdpu383_deinit() local
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H A Dhal_avs2d_rkv.c300 Avs2dRkvRegCtx_t *reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx; in hal_avs2d_rcb_info_update() local
304 RK_S32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1; in hal_avs2d_rcb_info_update()
308 reg_ctx->rcb_buf_size = vdpu34x_get_rcb_buf_size(reg_ctx->rcb_info, width, height); in hal_avs2d_rcb_info_update()
314 if (reg_ctx->rcb_buf[i]) { in hal_avs2d_rcb_info_update()
315 mpp_buffer_put(reg_ctx->rcb_buf[i]); in hal_avs2d_rcb_info_update()
316 reg_ctx->rcb_buf[i] = NULL; in hal_avs2d_rcb_info_update()
319 ret = mpp_buffer_get(p_hal->buf_group, &rcb_buf, reg_ctx->rcb_buf_size); in hal_avs2d_rcb_info_update()
324 reg_ctx->rcb_buf[i] = rcb_buf; in hal_avs2d_rcb_info_update()
479 Avs2dRkvRegCtx_t *reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx; in hal_avs2d_rkv_deinit() local
483 INP_CHECK(ret, NULL == reg_ctx); in hal_avs2d_rkv_deinit()
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H A Dhal_avs2d_vdpu382.c358 Avs2dVdpu382RegCtx_t *reg_ctx = (Avs2dVdpu382RegCtx_t *)p_hal->reg_ctx; in hal_avs2d_rcb_info_update() local
362 RK_S32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1; in hal_avs2d_rcb_info_update()
364 reg_ctx->rcb_buf_size = vdpu382_get_rcb_buf_size(reg_ctx->rcb_info, width, height); in hal_avs2d_rcb_info_update()
365 avs2d_refine_rcb_size(reg_ctx->rcb_info, hw_regs, width, height, (void *)&p_hal->syntax); in hal_avs2d_rcb_info_update()
370 if (reg_ctx->rcb_buf[i]) { in hal_avs2d_rcb_info_update()
371 mpp_buffer_put(reg_ctx->rcb_buf[i]); in hal_avs2d_rcb_info_update()
372 reg_ctx->rcb_buf[i] = NULL; in hal_avs2d_rcb_info_update()
375 ret = mpp_buffer_get(p_hal->buf_group, &rcb_buf, reg_ctx->rcb_buf_size); in hal_avs2d_rcb_info_update()
380 reg_ctx->rcb_buf[i] = rcb_buf; in hal_avs2d_rcb_info_update()
545 Avs2dVdpu382RegCtx_t *reg_ctx = (Avs2dVdpu382RegCtx_t *)p_hal->reg_ctx; in hal_avs2d_vdpu382_deinit() local
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H A Dhal_avs2d_global.h94 void *reg_ctx; member
/rockchip-linux_mpp/mpp/hal/rkdec/av1d/
H A Dhal_av1d_vdpu383.c1269 Vdpu383Av1dRegCtx *ctx = (Vdpu383Av1dRegCtx *)p_hal->reg_ctx; in vdpu383_setup_scale_origin_bufs()
1303 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Vdpu383Av1dRegCtx))); in hal_av1d_alloc_res()
1304 Vdpu383Av1dRegCtx *reg_ctx = (Vdpu383Av1dRegCtx *)p_hal->reg_ctx; in hal_av1d_alloc_res() local
1307 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->bufs, MPP_ALIGN(VDPU383_INFO_BUF_SIZE(ma… in hal_av1d_alloc_res()
1308 mpp_buffer_attach_dev(reg_ctx->bufs, p_hal->dev); in hal_av1d_alloc_res()
1309 reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs); in hal_av1d_alloc_res()
1310 reg_ctx->bufs_ptr = mpp_buffer_get_ptr(reg_ctx->bufs); in hal_av1d_alloc_res()
1314 reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu383Av1dRegSet, 1); in hal_av1d_alloc_res()
1315 memset(reg_ctx->reg_buf[i].regs, 0, sizeof(Vdpu383Av1dRegSet)); in hal_av1d_alloc_res()
1316 reg_ctx->uncmps_offset[i] = VDPU383_UNCMPS_HEADER_OFFSET(i); in hal_av1d_alloc_res()
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/rockchip-linux_mpp/mpp/hal/vpu/av1d/
H A Dhal_av1d_vdpu.c139 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(VdpuAv1dRegCtx))); in hal_av1d_alloc_res()
140 VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx; in hal_av1d_alloc_res() local
144 reg_ctx->reg_buf[i].regs = mpp_calloc(VdpuAv1dRegSet, 1); in hal_av1d_alloc_res()
145 memset(reg_ctx->reg_buf[i].regs, 0, sizeof(VdpuAv1dRegSet)); in hal_av1d_alloc_res()
149 reg_ctx->regs = reg_ctx->reg_buf[0].regs; in hal_av1d_alloc_res()
152 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->prob_tbl_base, MPP_ALIGN(sizeof(AV1CDFs)… in hal_av1d_alloc_res()
153 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->prob_tbl_out_base, MPP_ALIGN(sizeof(AV1C… in hal_av1d_alloc_res()
154 BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->tile_info, AV1_TILE_INFO_SIZE)); in hal_av1d_alloc_res()
155 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->film_grain_mem, MPP_ALIGN(sizeof(AV1Film… in hal_av1d_alloc_res()
156 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->global_model, MPP_ALIGN(GLOBAL_MODEL_SIZ… in hal_av1d_alloc_res()
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/rockchip-linux_mpp/mpp/hal/common/av1/
H A Dhal_av1d_common.h189 void *reg_ctx; member