Lines Matching refs:reg_ctx
45 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_alloc_res() local
46 if (reg_ctx->fast_mode) { in hal_h265d_alloc_res()
48 reg_ctx->g_buf[i].hw_regs = in hal_h265d_alloc_res()
50 ret = mpp_buffer_get(reg_ctx->group, in hal_h265d_alloc_res()
51 ®_ctx->g_buf[i].scaling_list_data, in hal_h265d_alloc_res()
58 ret = mpp_buffer_get(reg_ctx->group, ®_ctx->g_buf[i].pps_data, in hal_h265d_alloc_res()
65 ret = mpp_buffer_get(reg_ctx->group, ®_ctx->g_buf[i].rps_data, in hal_h265d_alloc_res()
73 reg_ctx->hw_regs = mpp_calloc_size(void, sizeof(H265d_REGS_t)); in hal_h265d_alloc_res()
74 ret = mpp_buffer_get(reg_ctx->group, ®_ctx->scaling_list_data, in hal_h265d_alloc_res()
81 ret = mpp_buffer_get(reg_ctx->group, ®_ctx->pps_data, PPS_SIZE); in hal_h265d_alloc_res()
87 ret = mpp_buffer_get(reg_ctx->group, ®_ctx->rps_data, RPS_SIZE); in hal_h265d_alloc_res()
100 HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal; in hal_h265d_release_res() local
102 if (reg_ctx->fast_mode) { in hal_h265d_release_res()
104 if (reg_ctx->g_buf[i].scaling_list_data) { in hal_h265d_release_res()
105 ret = mpp_buffer_put(reg_ctx->g_buf[i].scaling_list_data); in hal_h265d_release_res()
111 if (reg_ctx->g_buf[i].pps_data) { in hal_h265d_release_res()
112 ret = mpp_buffer_put(reg_ctx->g_buf[i].pps_data); in hal_h265d_release_res()
119 if (reg_ctx->g_buf[i].rps_data) { in hal_h265d_release_res()
120 ret = mpp_buffer_put(reg_ctx->g_buf[i].rps_data); in hal_h265d_release_res()
127 if (reg_ctx->g_buf[i].hw_regs) { in hal_h265d_release_res()
128 mpp_free(reg_ctx->g_buf[i].hw_regs); in hal_h265d_release_res()
129 reg_ctx->g_buf[i].hw_regs = NULL; in hal_h265d_release_res()
133 if (reg_ctx->scaling_list_data) { in hal_h265d_release_res()
134 ret = mpp_buffer_put(reg_ctx->scaling_list_data); in hal_h265d_release_res()
140 if (reg_ctx->pps_data) { in hal_h265d_release_res()
141 ret = mpp_buffer_put(reg_ctx->pps_data); in hal_h265d_release_res()
148 if (reg_ctx->rps_data) { in hal_h265d_release_res()
149 ret = mpp_buffer_put(reg_ctx->rps_data); in hal_h265d_release_res()
156 if (reg_ctx->hw_regs) { in hal_h265d_release_res()
157 mpp_free(reg_ctx->hw_regs); in hal_h265d_release_res()
158 reg_ctx->hw_regs = NULL; in hal_h265d_release_res()
167 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_rkv_init() local
169 mpp_slots_set_prop(reg_ctx->slots, SLOTS_HOR_ALIGN, hevc_hor_align); in hal_h265d_rkv_init()
170 mpp_slots_set_prop(reg_ctx->slots, SLOTS_VER_ALIGN, hevc_ver_align); in hal_h265d_rkv_init()
172 reg_ctx->scaling_qm = mpp_calloc(DXVA_Qmatrix_HEVC, 1); in hal_h265d_rkv_init()
173 reg_ctx->sw_rps_buf = mpp_calloc(RK_U64, 400); in hal_h265d_rkv_init()
175 if (reg_ctx->scaling_qm == NULL) { in hal_h265d_rkv_init()
180 reg_ctx->scaling_rk = mpp_calloc(scalingFactor_t, 1); in hal_h265d_rkv_init()
181 if (reg_ctx->scaling_rk == NULL) { in hal_h265d_rkv_init()
186 if (reg_ctx->group == NULL) { in hal_h265d_rkv_init()
187 ret = mpp_buffer_group_get_internal(®_ctx->group, MPP_BUFFER_TYPE_ION); in hal_h265d_rkv_init()
194 ret = mpp_buffer_get(reg_ctx->group, ®_ctx->cabac_table_data, sizeof(cabac_table)); in hal_h265d_rkv_init()
200 ret = mpp_buffer_write(reg_ctx->cabac_table_data, 0, (void*)cabac_table, sizeof(cabac_table)); in hal_h265d_rkv_init()
205 mpp_buffer_sync_end(reg_ctx->cabac_table_data); in hal_h265d_rkv_init()
223 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_rkv_deinit() local
225 ret = mpp_buffer_put(reg_ctx->cabac_table_data); in hal_h265d_rkv_deinit()
231 if (reg_ctx->scaling_qm) { in hal_h265d_rkv_deinit()
232 mpp_free(reg_ctx->scaling_qm); in hal_h265d_rkv_deinit()
235 if (reg_ctx->sw_rps_buf) { in hal_h265d_rkv_deinit()
236 mpp_free(reg_ctx->sw_rps_buf); in hal_h265d_rkv_deinit()
239 if (reg_ctx->scaling_rk) { in hal_h265d_rkv_deinit()
240 mpp_free(reg_ctx->scaling_rk); in hal_h265d_rkv_deinit()
245 if (reg_ctx->group) { in hal_h265d_rkv_deinit()
246 ret = mpp_buffer_group_put(reg_ctx->group); in hal_h265d_rkv_deinit()
261 HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal; in hal_h265d_v345_output_pps_packet() local
266 if (NULL == reg_ctx || dxva_cxt == NULL) { in hal_h265d_v345_output_pps_packet()
273 void *pps_ptr = mpp_buffer_get_ptr(reg_ctx->pps_data); in hal_h265d_v345_output_pps_packet()
446 RK_U8 *ptr_scaling = (RK_U8 *)mpp_buffer_get_ptr(reg_ctx->scaling_list_data); in hal_h265d_v345_output_pps_packet()
447 RK_U32 fd = mpp_buffer_get_fd(reg_ctx->scaling_list_data); in hal_h265d_v345_output_pps_packet()
475 HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal; in hal_h265d_output_pps_packet() local
480 if (NULL == reg_ctx || dxva_cxt == NULL) { in hal_h265d_output_pps_packet()
487 void *pps_ptr = mpp_buffer_get_ptr(reg_ctx->pps_data); in hal_h265d_output_pps_packet()
659 RK_U8 *ptr_scaling = (RK_U8 *)mpp_buffer_get_ptr(reg_ctx->scaling_list_data); in hal_h265d_output_pps_packet()
660 RK_U32 fd = mpp_buffer_get_fd(reg_ctx->scaling_list_data); in hal_h265d_output_pps_packet()
739 HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal; in hal_h265d_rkv_gen_regs() local
743 (syn->dec.flags.ref_err && !reg_ctx->cfg->base.disable_error)) { in hal_h265d_rkv_gen_regs()
752 if (reg_ctx ->fast_mode) { in hal_h265d_rkv_gen_regs()
754 if (!reg_ctx->g_buf[i].use_flag) { in hal_h265d_rkv_gen_regs()
756 reg_ctx->rps_data = reg_ctx->g_buf[i].rps_data; in hal_h265d_rkv_gen_regs()
757 reg_ctx->scaling_list_data = in hal_h265d_rkv_gen_regs()
758 reg_ctx->g_buf[i].scaling_list_data; in hal_h265d_rkv_gen_regs()
759 reg_ctx->pps_data = reg_ctx->g_buf[i].pps_data; in hal_h265d_rkv_gen_regs()
760 reg_ctx->hw_regs = reg_ctx->g_buf[i].hw_regs; in hal_h265d_rkv_gen_regs()
761 reg_ctx->g_buf[i].use_flag = 1; in hal_h265d_rkv_gen_regs()
772 rps_ptr = mpp_buffer_get_ptr(reg_ctx->rps_data); in hal_h265d_rkv_gen_regs()
786 if (reg_ctx->is_v345) { in hal_h265d_rkv_gen_regs()
792 if (NULL == reg_ctx->hw_regs) { in hal_h265d_rkv_gen_regs()
796 hw_regs = (H265d_REGS_t*)reg_ctx->hw_regs; in hal_h265d_rkv_gen_regs()
799 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_cxt->pp.CurrPic.Index7Bits, in hal_h265d_rkv_gen_regs()
812 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_cxt->pp.CurrPic.Index7Bits, in hal_h265d_rkv_gen_regs()
825 mpp_buf_slot_get_prop(reg_ctx->packet_slots, syn->dec.input, SLOT_BUFFER, in hal_h265d_rkv_gen_regs()
831 if (reg_ctx->is_v345) { in hal_h265d_rkv_gen_regs()
835 … hal_h265d_slice_hw_rps(syn->dec.syntax.data, rps_ptr, reg_ctx->sw_rps_buf, reg_ctx->fast_mode); in hal_h265d_rkv_gen_regs()
844 if (dxva_cxt->pp.slice_segment_header_extension_present_flag && !reg_ctx->is_v345) { in hal_h265d_rkv_gen_regs()
849 hw_regs->sw_cabactbl_base = mpp_buffer_get_fd(reg_ctx->cabac_table_data); in hal_h265d_rkv_gen_regs()
850 hw_regs->sw_pps_base = mpp_buffer_get_fd(reg_ctx->pps_data); in hal_h265d_rkv_gen_regs()
851 hw_regs->sw_rps_base = mpp_buffer_get_fd(reg_ctx->rps_data); in hal_h265d_rkv_gen_regs()
879 mpp_buf_slot_get_prop(reg_ctx->slots, in hal_h265d_rkv_gen_regs()
895 mpp_dev_set_reg_offset(reg_ctx->dev, 10, sw_ref_valid & 0xf); in hal_h265d_rkv_gen_regs()
896 mpp_dev_set_reg_offset(reg_ctx->dev, 11, ((sw_ref_valid >> 4) & 0xf)); in hal_h265d_rkv_gen_regs()
897 mpp_dev_set_reg_offset(reg_ctx->dev, 12, ((sw_ref_valid >> 8) & 0xf)); in hal_h265d_rkv_gen_regs()
898 mpp_dev_set_reg_offset(reg_ctx->dev, 13, ((sw_ref_valid >> 12) & 0xf)); in hal_h265d_rkv_gen_regs()
900 mpp_buffer_sync_end(reg_ctx->scaling_list_data); in hal_h265d_rkv_gen_regs()
901 mpp_buffer_sync_end(reg_ctx->pps_data); in hal_h265d_rkv_gen_regs()
902 mpp_buffer_sync_end(reg_ctx->rps_data); in hal_h265d_rkv_gen_regs()
911 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_rkv_start() local
917 (task->dec.flags.ref_err && !reg_ctx->cfg->base.disable_error)) { in hal_h265d_rkv_start()
922 if (reg_ctx->fast_mode) { in hal_h265d_rkv_start()
923 hw_regs = ( H265d_REGS_t *)reg_ctx->g_buf[index].hw_regs; in hal_h265d_rkv_start()
925 hw_regs = ( H265d_REGS_t *)reg_ctx->hw_regs; in hal_h265d_rkv_start()
937 RK_U32 reg_size = (reg_ctx->is_v341 || reg_ctx->is_v345) ? V345_HEVC_REGISTERS : in hal_h265d_rkv_start()
938 (reg_ctx->client_type == VPU_CLIENT_RKVDEC) ? in hal_h265d_rkv_start()
952 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_rkv_start()
962 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_h265d_rkv_start()
968 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_CMD_SEND, NULL); in hal_h265d_rkv_start()
982 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_rkv_wait() local
986 if (reg_ctx->fast_mode) { in hal_h265d_rkv_wait()
987 hw_regs = ( H265d_REGS_t *)reg_ctx->g_buf[index].hw_regs; in hal_h265d_rkv_wait()
989 hw_regs = ( H265d_REGS_t *)reg_ctx->hw_regs; in hal_h265d_rkv_wait()
993 (task->dec.flags.ref_err && !reg_ctx->cfg->base.disable_error)) { in hal_h265d_rkv_wait()
998 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_CMD_POLL, NULL); in hal_h265d_rkv_wait()
1008 if (!reg_ctx->fast_mode) { in hal_h265d_rkv_wait()
1009 if (reg_ctx->dec_cb) in hal_h265d_rkv_wait()
1010 mpp_callback(reg_ctx->dec_cb, &task->dec); in hal_h265d_rkv_wait()
1013 mpp_buf_slot_get_prop(reg_ctx->slots, task->dec.output, in hal_h265d_rkv_wait()
1016 reg_ctx->fast_mode_err_found = 1; in hal_h265d_rkv_wait()
1021 if (reg_ctx->fast_mode && reg_ctx->fast_mode_err_found) { in hal_h265d_rkv_wait()
1026 mpp_buf_slot_get_prop(reg_ctx->slots, task->dec.refer[i], in hal_h265d_rkv_wait()
1032 mpp_buf_slot_get_prop(reg_ctx->slots, task->dec.output, in hal_h265d_rkv_wait()
1046 if (reg_ctx->fast_mode) { in hal_h265d_rkv_wait()
1047 reg_ctx->g_buf[index].use_flag = 0; in hal_h265d_rkv_wait()