Lines Matching refs:reg_ctx
112 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu383_init() local
114 mpp_slots_set_prop(reg_ctx->slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64); in hal_h265d_vdpu383_init()
115 mpp_slots_set_prop(reg_ctx->slots, SLOTS_VER_ALIGN, hevc_ver_align); in hal_h265d_vdpu383_init()
117 reg_ctx->scaling_qm = mpp_calloc(DXVA_Qmatrix_HEVC, 1); in hal_h265d_vdpu383_init()
118 if (reg_ctx->scaling_qm == NULL) { in hal_h265d_vdpu383_init()
123 reg_ctx->scaling_rk = mpp_calloc(scalingFactor_t, 1); in hal_h265d_vdpu383_init()
124 reg_ctx->pps_buf = mpp_calloc(RK_U64, 24); in hal_h265d_vdpu383_init()
125 reg_ctx->sw_rps_buf = mpp_calloc(RK_U64, 400); in hal_h265d_vdpu383_init()
127 if (reg_ctx->scaling_rk == NULL) { in hal_h265d_vdpu383_init()
132 if (reg_ctx->group == NULL) { in hal_h265d_vdpu383_init()
133 ret = mpp_buffer_group_get_internal(®_ctx->group, MPP_BUFFER_TYPE_ION); in hal_h265d_vdpu383_init()
142 RK_U32 max_cnt = reg_ctx->fast_mode ? MAX_GEN_REG : 1; in hal_h265d_vdpu383_init()
145 ret = mpp_buffer_get(reg_ctx->group, ®_ctx->bufs, ALL_BUFFER_SIZE(max_cnt)); in hal_h265d_vdpu383_init()
151 reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs); in hal_h265d_vdpu383_init()
152 reg_ctx->offset_cabac = CABAC_TAB_OFFSET; in hal_h265d_vdpu383_init()
154 reg_ctx->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(Vdpu383H265dRegSet)); in hal_h265d_vdpu383_init()
155 reg_ctx->offset_spspps[i] = SPSPPS_OFFSET(i); in hal_h265d_vdpu383_init()
156 reg_ctx->offset_rps[i] = RPS_OFFSET(i); in hal_h265d_vdpu383_init()
157 reg_ctx->offset_sclst[i] = SCALIST_OFFSET(i); in hal_h265d_vdpu383_init()
160 mpp_buffer_attach_dev(reg_ctx->bufs, reg_ctx->dev); in hal_h265d_vdpu383_init()
163 if (!reg_ctx->fast_mode) { in hal_h265d_vdpu383_init()
164 reg_ctx->hw_regs = reg_ctx->g_buf[0].hw_regs; in hal_h265d_vdpu383_init()
165 reg_ctx->spspps_offset = reg_ctx->offset_spspps[0]; in hal_h265d_vdpu383_init()
166 reg_ctx->rps_offset = reg_ctx->offset_rps[0]; in hal_h265d_vdpu383_init()
167 reg_ctx->sclst_offset = reg_ctx->offset_sclst[0]; in hal_h265d_vdpu383_init()
170 ret = mpp_buffer_write(reg_ctx->bufs, 0, (void*)cabac_table, sizeof(cabac_table)); in hal_h265d_vdpu383_init()
187 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu383_deinit() local
188 RK_U32 loop = reg_ctx->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->g_buf) : 1; in hal_h265d_vdpu383_deinit()
191 if (reg_ctx->bufs) { in hal_h265d_vdpu383_deinit()
192 mpp_buffer_put(reg_ctx->bufs); in hal_h265d_vdpu383_deinit()
193 reg_ctx->bufs = NULL; in hal_h265d_vdpu383_deinit()
196 loop = reg_ctx->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->rcb_buf) : 1; in hal_h265d_vdpu383_deinit()
198 if (reg_ctx->rcb_buf[i]) { in hal_h265d_vdpu383_deinit()
199 mpp_buffer_put(reg_ctx->rcb_buf[i]); in hal_h265d_vdpu383_deinit()
200 reg_ctx->rcb_buf[i] = NULL; in hal_h265d_vdpu383_deinit()
204 if (reg_ctx->group) { in hal_h265d_vdpu383_deinit()
205 mpp_buffer_group_put(reg_ctx->group); in hal_h265d_vdpu383_deinit()
206 reg_ctx->group = NULL; in hal_h265d_vdpu383_deinit()
210 MPP_FREE(reg_ctx->g_buf[i].hw_regs); in hal_h265d_vdpu383_deinit()
212 MPP_FREE(reg_ctx->scaling_qm); in hal_h265d_vdpu383_deinit()
213 MPP_FREE(reg_ctx->scaling_rk); in hal_h265d_vdpu383_deinit()
214 MPP_FREE(reg_ctx->pps_buf); in hal_h265d_vdpu383_deinit()
215 MPP_FREE(reg_ctx->sw_rps_buf); in hal_h265d_vdpu383_deinit()
217 if (reg_ctx->cmv_bufs) { in hal_h265d_vdpu383_deinit()
218 hal_bufs_deinit(reg_ctx->cmv_bufs); in hal_h265d_vdpu383_deinit()
219 reg_ctx->cmv_bufs = NULL; in hal_h265d_vdpu383_deinit()
222 if (reg_ctx->origin_bufs) { in hal_h265d_vdpu383_deinit()
223 hal_bufs_deinit(reg_ctx->origin_bufs); in hal_h265d_vdpu383_deinit()
224 reg_ctx->origin_bufs = NULL; in hal_h265d_vdpu383_deinit()
331 HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal; in hal_h265d_vdpu383_scalinglist_packet() local
337 if (memcmp((void*)&dxva_ctx->qm, reg_ctx->scaling_qm, sizeof(DXVA_Qmatrix_HEVC))) { in hal_h265d_vdpu383_scalinglist_packet()
367 hal_vdpu383_record_scaling_list((scalingFactor_t *)reg_ctx->scaling_rk, &sl); in hal_h265d_vdpu383_scalinglist_packet()
370 memcpy(ptr, reg_ctx->scaling_rk, sizeof(scalingFactor_t)); in hal_h265d_vdpu383_scalinglist_packet()
380 HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal; in hal_h265d_v345_output_pps_packet() local
381 Vdpu383H265dRegSet *hw_reg = (Vdpu383H265dRegSet*)(reg_ctx->hw_regs); in hal_h265d_v345_output_pps_packet()
385 if (NULL == reg_ctx || dxva_ctx == NULL) { in hal_h265d_v345_output_pps_packet()
393 void *pps_ptr = mpp_buffer_get_ptr(reg_ctx->bufs) + reg_ctx->spspps_offset; in hal_h265d_v345_output_pps_packet()
394 RK_U64 *pps_packet = reg_ctx->pps_buf; in hal_h265d_v345_output_pps_packet()
609 memcpy(pps_ptr, reg_ctx->pps_buf, 176); in hal_h265d_v345_output_pps_packet()
614 RK_U8 *ptr_scaling = (RK_U8 *)mpp_buffer_get_ptr(reg_ctx->bufs) + reg_ctx->sclst_offset; in hal_h265d_v345_output_pps_packet()
626 hw_reg->common_addr.reg132_scanlist_addr = reg_ctx->bufs_fd; in hal_h265d_v345_output_pps_packet()
627 mpp_dev_set_reg_offset(reg_ctx->dev, 132, addr + reg_ctx->sclst_offset); in hal_h265d_v345_output_pps_packet()
729 HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal; in hal_h265d_rcb_info_update() local
738 if (reg_ctx->num_row_tiles != num_tiles || in hal_h265d_rcb_info_update()
739 reg_ctx->bit_depth != bit_depth || in hal_h265d_rcb_info_update()
740 reg_ctx->chroma_fmt_idc != chroma_fmt_idc || in hal_h265d_rcb_info_update()
741 reg_ctx->ctu_size != ctu_size || in hal_h265d_rcb_info_update()
742 reg_ctx->width != width || in hal_h265d_rcb_info_update()
743 reg_ctx->height != height) { in hal_h265d_rcb_info_update()
745 RK_U32 loop = reg_ctx->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->g_buf) : 1; in hal_h265d_rcb_info_update()
747 …reg_ctx->rcb_buf_size = vdpu383_get_rcb_buf_size((Vdpu383RcbInfo *)reg_ctx->rcb_info, width, heigh… in hal_h265d_rcb_info_update()
748 h265d_refine_rcb_size((Vdpu383RcbInfo *)reg_ctx->rcb_info, width, height, dxva_ctx); in hal_h265d_rcb_info_update()
753 if (reg_ctx->rcb_buf[i]) { in hal_h265d_rcb_info_update()
754 mpp_buffer_put(reg_ctx->rcb_buf[i]); in hal_h265d_rcb_info_update()
755 reg_ctx->rcb_buf[i] = NULL; in hal_h265d_rcb_info_update()
757 mpp_buffer_get(reg_ctx->group, &rcb_buf, reg_ctx->rcb_buf_size); in hal_h265d_rcb_info_update()
758 reg_ctx->rcb_buf[i] = rcb_buf; in hal_h265d_rcb_info_update()
761 reg_ctx->num_row_tiles = num_tiles; in hal_h265d_rcb_info_update()
762 reg_ctx->bit_depth = bit_depth; in hal_h265d_rcb_info_update()
763 reg_ctx->chroma_fmt_idc = chroma_fmt_idc; in hal_h265d_rcb_info_update()
764 reg_ctx->ctu_size = ctu_size; in hal_h265d_rcb_info_update()
765 reg_ctx->width = width; in hal_h265d_rcb_info_update()
766 reg_ctx->height = height; in hal_h265d_rcb_info_update()
872 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu383_gen_regs() local
876 (syn->dec.flags.ref_err && !reg_ctx->cfg->base.disable_error)) { in hal_h265d_vdpu383_gen_regs()
885 if (reg_ctx ->fast_mode) { in hal_h265d_vdpu383_gen_regs()
887 if (!reg_ctx->g_buf[i].use_flag) { in hal_h265d_vdpu383_gen_regs()
890 reg_ctx->spspps_offset = reg_ctx->offset_spspps[i]; in hal_h265d_vdpu383_gen_regs()
891 reg_ctx->rps_offset = reg_ctx->offset_rps[i]; in hal_h265d_vdpu383_gen_regs()
892 reg_ctx->sclst_offset = reg_ctx->offset_sclst[i]; in hal_h265d_vdpu383_gen_regs()
894 reg_ctx->hw_regs = reg_ctx->g_buf[i].hw_regs; in hal_h265d_vdpu383_gen_regs()
895 reg_ctx->g_buf[i].use_flag = 1; in hal_h265d_vdpu383_gen_regs()
904 rps_ptr = mpp_buffer_get_ptr(reg_ctx->bufs) + reg_ctx->rps_offset; in hal_h265d_vdpu383_gen_regs()
930 hw_regs = (Vdpu383H265dRegSet*)reg_ctx->hw_regs; in hal_h265d_vdpu383_gen_regs()
933 if (NULL == reg_ctx->hw_regs) { in hal_h265d_vdpu383_gen_regs()
943 if (reg_ctx->cmv_bufs == NULL || reg_ctx->mv_size < mv_size) { in hal_h265d_vdpu383_gen_regs()
946 if (reg_ctx->cmv_bufs) { in hal_h265d_vdpu383_gen_regs()
947 hal_bufs_deinit(reg_ctx->cmv_bufs); in hal_h265d_vdpu383_gen_regs()
948 reg_ctx->cmv_bufs = NULL; in hal_h265d_vdpu383_gen_regs()
951 hal_bufs_init(®_ctx->cmv_bufs); in hal_h265d_vdpu383_gen_regs()
952 if (reg_ctx->cmv_bufs == NULL) { in hal_h265d_vdpu383_gen_regs()
957 reg_ctx->mv_size = mv_size; in hal_h265d_vdpu383_gen_regs()
958 reg_ctx->mv_count = mpp_buf_slot_get_count(reg_ctx->slots); in hal_h265d_vdpu383_gen_regs()
959 hal_bufs_setup(reg_ctx->cmv_bufs, reg_ctx->mv_count, 1, &size); in hal_h265d_vdpu383_gen_regs()
969 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_ctx->pp.CurrPic.Index7Bits, in hal_h265d_vdpu383_gen_regs()
973 reg_ctx->origin_bufs == NULL) { in hal_h265d_vdpu383_gen_regs()
974 vdpu383_setup_scale_origin_bufs(reg_ctx, mframe); in hal_h265d_vdpu383_gen_regs()
1020 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_ctx->pp.CurrPic.Index7Bits, in hal_h265d_vdpu383_gen_regs()
1023 if (reg_ctx->origin_bufs) { in hal_h265d_vdpu383_gen_regs()
1024 origin_buf = hal_bufs_get_buf(reg_ctx->origin_bufs, in hal_h265d_vdpu383_gen_regs()
1041 mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, dxva_ctx->pp.CurrPic.Index7Bits); in hal_h265d_vdpu383_gen_regs()
1054 mpp_buf_slot_get_prop(reg_ctx->packet_slots, syn->dec.input, SLOT_BUFFER, in hal_h265d_vdpu383_gen_regs()
1070 hal_h265d_vdpu383_rps(syn->dec.syntax.data, rps_ptr, reg_ctx->sw_rps_buf, reg_ctx->fast_mode); in hal_h265d_vdpu383_gen_regs()
1106 reg_ctx->error_index[syn->dec.reg_index] = dxva_ctx->pp.CurrPic.Index7Bits; in hal_h265d_vdpu383_gen_regs()
1114 mpp_buf_slot_get_prop(reg_ctx->slots, in hal_h265d_vdpu383_gen_regs()
1117 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_ctx->pp.RefPicList[i].Index7Bits, in hal_h265d_vdpu383_gen_regs()
1120 origin_buf = hal_bufs_get_buf(reg_ctx->origin_bufs, in hal_h265d_vdpu383_gen_regs()
1133 … reg_ctx->error_index[syn->dec.reg_index] = dxva_ctx->pp.RefPicList[i].Index7Bits; in hal_h265d_vdpu383_gen_regs()
1141 mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, dxva_ctx->pp.RefPicList[i].Index7Bits); in hal_h265d_vdpu383_gen_regs()
1146 if ((reg_ctx->error_index[syn->dec.reg_index] == dxva_ctx->pp.CurrPic.Index7Bits) && in hal_h265d_vdpu383_gen_regs()
1154 hw_regs->common_addr.reg131_gbl_base = reg_ctx->bufs_fd; in hal_h265d_vdpu383_gen_regs()
1156 mpp_dev_set_reg_offset(reg_ctx->dev, 131, reg_ctx->spspps_offset); in hal_h265d_vdpu383_gen_regs()
1159 hw_regs->common_addr.reg129_rps_base = reg_ctx->bufs_fd; in hal_h265d_vdpu383_gen_regs()
1160 mpp_dev_set_reg_offset(reg_ctx->dev, 129, reg_ctx->rps_offset); in hal_h265d_vdpu383_gen_regs()
1170 mpp_buf_slot_get_prop(reg_ctx->slots, in hal_h265d_vdpu383_gen_regs()
1174 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_ctx->pp.RefPicList[i].Index7Bits, in hal_h265d_vdpu383_gen_regs()
1178 … mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index[syn->dec.reg_index]); in hal_h265d_vdpu383_gen_regs()
1184 mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index[syn->dec.reg_index]); in hal_h265d_vdpu383_gen_regs()
1192 vdpu383_setup_rcb(&hw_regs->common_addr, reg_ctx->dev, reg_ctx->fast_mode ? in hal_h265d_vdpu383_gen_regs()
1193 reg_ctx->rcb_buf[syn->dec.reg_index] : reg_ctx->rcb_buf[0], in hal_h265d_vdpu383_gen_regs()
1194 (Vdpu383RcbInfo *)reg_ctx->rcb_info); in hal_h265d_vdpu383_gen_regs()
1196 mpp_buffer_sync_end(reg_ctx->bufs); in hal_h265d_vdpu383_gen_regs()
1204 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_ctx->pp.CurrPic.Index7Bits, in hal_h265d_vdpu383_gen_regs()
1206 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_ctx->pp.CurrPic.Index7Bits, in hal_h265d_vdpu383_gen_regs()
1212 origin_buf = hal_bufs_get_buf(reg_ctx->origin_bufs, dxva_ctx->pp.CurrPic.Index7Bits); in hal_h265d_vdpu383_gen_regs()
1217 … vdpu383_setup_down_scale(mframe, reg_ctx->dev, &hw_regs->ctrl_regs, (void*)&hw_regs->h265d_paras); in hal_h265d_vdpu383_gen_regs()
1221 … vdpu383_setup_down_scale(mframe, reg_ctx->dev, &hw_regs->ctrl_regs, (void*)&hw_regs->h265d_paras); in hal_h265d_vdpu383_gen_regs()
1238 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu383_start() local
1244 (task->dec.flags.ref_err && !reg_ctx->cfg->base.disable_error)) { in hal_h265d_vdpu383_start()
1249 if (reg_ctx->fast_mode) { in hal_h265d_vdpu383_start()
1250 p = (RK_U8*)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu383_start()
1251 hw_regs = ( Vdpu383H265dRegSet *)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu383_start()
1253 p = (RK_U8*)reg_ctx->hw_regs; in hal_h265d_vdpu383_start()
1254 hw_regs = ( Vdpu383H265dRegSet *)reg_ctx->hw_regs; in hal_h265d_vdpu383_start()
1275 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu383_start()
1284 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu383_start()
1293 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu383_start()
1302 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu383_start()
1311 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_h265d_vdpu383_start()
1318 vdpu383_set_rcbinfo(reg_ctx->dev, (Vdpu383RcbInfo*)reg_ctx->rcb_info); in hal_h265d_vdpu383_start()
1320 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_CMD_SEND, NULL); in hal_h265d_vdpu383_start()
1335 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu383_wait() local
1340 if (reg_ctx->fast_mode) { in hal_h265d_vdpu383_wait()
1341 hw_regs = ( Vdpu383H265dRegSet *)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu383_wait()
1343 hw_regs = ( Vdpu383H265dRegSet *)reg_ctx->hw_regs; in hal_h265d_vdpu383_wait()
1349 (task->dec.flags.ref_err && !reg_ctx->cfg->base.disable_error)) { in hal_h265d_vdpu383_wait()
1354 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_CMD_POLL, NULL); in hal_h265d_vdpu383_wait()
1368 if (!reg_ctx->fast_mode) { in hal_h265d_vdpu383_wait()
1369 if (reg_ctx->dec_cb) in hal_h265d_vdpu383_wait()
1370 mpp_callback(reg_ctx->dec_cb, &task->dec); in hal_h265d_vdpu383_wait()
1373 mpp_buf_slot_get_prop(reg_ctx->slots, task->dec.output, in hal_h265d_vdpu383_wait()
1376 reg_ctx->fast_mode_err_found = 1; in hal_h265d_vdpu383_wait()
1381 if (reg_ctx->fast_mode && reg_ctx->fast_mode_err_found) { in hal_h265d_vdpu383_wait()
1386 mpp_buf_slot_get_prop(reg_ctx->slots, task->dec.refer[i], in hal_h265d_vdpu383_wait()
1392 mpp_buf_slot_get_prop(reg_ctx->slots, task->dec.output, in hal_h265d_vdpu383_wait()
1415 if (reg_ctx->fast_mode) { in hal_h265d_vdpu383_wait()
1416 reg_ctx->g_buf[index].use_flag = 0; in hal_h265d_vdpu383_wait()