Lines Matching refs:reg_ctx
132 Vdpu383H264dRegCtx *ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx; in vdpu383_setup_scale_origin_bufs()
420 Vdpu383H264dRegCtx *ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx; in set_registers()
532 Vdpu383H264dRegCtx *reg_ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx; in set_registers() local
547 regs->common_addr.reg130_cabactbl_base = reg_ctx->bufs_fd; in set_registers()
548 mpp_dev_set_reg_offset(p_hal->dev, 130, reg_ctx->offset_cabac); in set_registers()
637 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Vdpu383H264dRegCtx))); in vdpu383_h264d_init()
638 Vdpu383H264dRegCtx *reg_ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx; in vdpu383_h264d_init() local
643 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, ®_ctx->bufs, in vdpu383_h264d_init()
645 reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs); in vdpu383_h264d_init()
646 reg_ctx->bufs_ptr = mpp_buffer_get_ptr(reg_ctx->bufs); in vdpu383_h264d_init()
647 reg_ctx->offset_cabac = VDPU383_CABAC_TAB_OFFSET; in vdpu383_h264d_init()
648 reg_ctx->offset_errinfo = VDPU383_ERROR_INFO_OFFSET; in vdpu383_h264d_init()
650 reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu383H264dRegSet, 1); in vdpu383_h264d_init()
651 init_ctrl_regs(reg_ctx->reg_buf[i].regs); in vdpu383_h264d_init()
652 reg_ctx->offset_spspps[i] = VDPU383_SPSPPS_OFFSET(i); in vdpu383_h264d_init()
653 reg_ctx->offset_rps[i] = VDPU383_RPS_OFFSET(i); in vdpu383_h264d_init()
654 reg_ctx->offset_sclst[i] = VDPU383_SCALING_LIST_OFFSET(i); in vdpu383_h264d_init()
657 mpp_buffer_attach_dev(reg_ctx->bufs, p_hal->dev); in vdpu383_h264d_init()
660 reg_ctx->regs = reg_ctx->reg_buf[0].regs; in vdpu383_h264d_init()
661 reg_ctx->spspps_offset = reg_ctx->offset_spspps[0]; in vdpu383_h264d_init()
662 reg_ctx->rps_offset = reg_ctx->offset_rps[0]; in vdpu383_h264d_init()
663 reg_ctx->sclst_offset = reg_ctx->offset_sclst[0]; in vdpu383_h264d_init()
667 memcpy((char *)reg_ctx->bufs_ptr + reg_ctx->offset_cabac, in vdpu383_h264d_init()
690 Vdpu383H264dRegCtx *reg_ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx; in vdpu383_h264d_deinit() local
693 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1; in vdpu383_h264d_deinit()
695 if (reg_ctx->bufs) { in vdpu383_h264d_deinit()
696 mpp_buffer_put(reg_ctx->bufs); in vdpu383_h264d_deinit()
697 reg_ctx->bufs = NULL; in vdpu383_h264d_deinit()
701 MPP_FREE(reg_ctx->reg_buf[i].regs); in vdpu383_h264d_deinit()
703 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->rcb_buf) : 1; in vdpu383_h264d_deinit()
705 if (reg_ctx->rcb_buf[i]) { in vdpu383_h264d_deinit()
706 mpp_buffer_put(reg_ctx->rcb_buf[i]); in vdpu383_h264d_deinit()
707 reg_ctx->rcb_buf[i] = NULL; in vdpu383_h264d_deinit()
716 if (reg_ctx->origin_bufs) { in vdpu383_h264d_deinit()
717 hal_bufs_deinit(reg_ctx->origin_bufs); in vdpu383_h264d_deinit()
718 reg_ctx->origin_bufs = NULL; in vdpu383_h264d_deinit()
721 MPP_FREE(p_hal->reg_ctx); in vdpu383_h264d_deinit()
780 Vdpu383H264dRegCtx *ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx; in hal_h264d_rcb_info_update()
818 Vdpu383H264dRegCtx *ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx; in vdpu383_h264d_gen_regs()
932 Vdpu383H264dRegCtx *reg_ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx; in vdpu383_h264d_start() local
934 reg_ctx->reg_buf[task->dec.reg_index].regs : in vdpu383_h264d_start()
935 reg_ctx->regs; in vdpu383_h264d_start()
988 vdpu383_set_rcbinfo(dev, (Vdpu383RcbInfo*)reg_ctx->rcb_info); in vdpu383_h264d_start()
1008 Vdpu383H264dRegCtx *reg_ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx; in vdpu383_h264d_wait() local
1010 reg_ctx->reg_buf[task->dec.reg_index].regs : in vdpu383_h264d_wait()
1011 reg_ctx->regs; in vdpu383_h264d_wait()
1044 reg_ctx->reg_buf[task->dec.reg_index].valid = 0; in vdpu383_h264d_wait()