1 /*
2 * Copyright 2022 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_avs2d_vdpu382"
18
19 #include <string.h>
20 #include <stdio.h>
21
22 #include "mpp_log.h"
23 #include "mpp_mem.h"
24 #include "mpp_common.h"
25 #include "mpp_debug.h"
26 #include "mpp_bitput.h"
27
28 #include "avs2d_syntax.h"
29 #include "hal_avs2d_api.h"
30 #include "hal_avs2d_vdpu382.h"
31 #include "mpp_dec_cb_param.h"
32 #include "vdpu382_avs2d.h"
33
34 #define VDPU382_FAST_REG_SET_CNT (3)
35 #define MAX_REF_NUM (8)
36 #define AVS2_RKV_SHPH_SIZE (1408 / 8) /* bytes */
37 #define AVS2_RKV_SCALIST_SIZE (80 + 128) /* bytes */
38 #define VDPU382_TOTAL_REG_CNT (278)
39
40 #define AVS2_RKV_SHPH_ALIGNED_SIZE (MPP_ALIGN(AVS2_RKV_SHPH_SIZE, SZ_4K))
41 #define AVS2_RKV_SCALIST_ALIGNED_SIZE (MPP_ALIGN(AVS2_RKV_SCALIST_SIZE, SZ_4K))
42 #define AVS2_RKV_STREAM_INFO_SET_SIZE (AVS2_RKV_SHPH_ALIGNED_SIZE + \
43 AVS2_RKV_SCALIST_ALIGNED_SIZE)
44 #define AVS2_ALL_TBL_BUF_SIZE(cnt) (AVS2_RKV_STREAM_INFO_SET_SIZE * (cnt))
45 #define AVS2_SHPH_OFFSET(pos) (AVS2_RKV_STREAM_INFO_SET_SIZE * (pos))
46 #define AVS2_SCALIST_OFFSET(pos) (AVS2_SHPH_OFFSET(pos) + AVS2_RKV_SHPH_ALIGNED_SIZE)
47
48 #define COLMV_COMPRESS_EN (1)
49 #define COLMV_BLOCK_SIZE (16)
50 #define COLMV_BYTES (16)
51
52 typedef struct avs2d_buf_t {
53 RK_U32 valid;
54 RK_U32 offset_shph;
55 RK_U32 offset_sclst;
56 Vdpu382Avs2dRegSet *regs;
57 } Avs2dVdpu382Buf_t;
58
59 typedef struct avs2d_reg_ctx_t {
60 Avs2dVdpu382Buf_t reg_buf[VDPU382_FAST_REG_SET_CNT];
61
62 RK_U32 shph_offset;
63 RK_U32 sclst_offset;
64
65 Vdpu382Avs2dRegSet *regs;
66
67 RK_U8 shph_dat[AVS2_RKV_SHPH_SIZE];
68 RK_U8 scalist_dat[AVS2_RKV_SCALIST_SIZE];
69
70 MppBuffer bufs;
71 RK_S32 bufs_fd;
72 void *bufs_ptr;
73
74 MppBuffer rcb_buf[VDPU382_FAST_REG_SET_CNT];
75 RK_S32 rcb_buf_size;
76 Vdpu382RcbInfo rcb_info[RCB_BUF_COUNT];
77 RK_U32 reg_out[VDPU382_TOTAL_REG_CNT];
78
79 } Avs2dVdpu382RegCtx_t;
80
81 MPP_RET hal_avs2d_vdpu382_deinit(void *hal);
avs2d_ver_align(RK_U32 val)82 static RK_U32 avs2d_ver_align(RK_U32 val)
83 {
84 return MPP_ALIGN(val, 16);
85 }
86
avs2d_hor_align(RK_U32 val)87 static RK_U32 avs2d_hor_align(RK_U32 val)
88 {
89
90 return MPP_ALIGN(val, 16);
91 }
92
avs2d_len_align(RK_U32 val)93 static RK_U32 avs2d_len_align(RK_U32 val)
94 {
95 return (2 * MPP_ALIGN(val, 16));
96 }
97
avs2d_hor_align_64(RK_U32 val)98 static RK_U32 avs2d_hor_align_64(RK_U32 val)
99 {
100 return MPP_ALIGN(val, 64);
101 }
102
prepare_header(Avs2dHalCtx_t * p_hal,RK_U8 * data,RK_U32 len)103 static MPP_RET prepare_header(Avs2dHalCtx_t *p_hal, RK_U8 *data, RK_U32 len)
104 {
105 RK_U32 i, j;
106 BitputCtx_t bp;
107 RK_U64 *bit_buf = (RK_U64 *)data;
108 Avs2dSyntax_t *syntax = &p_hal->syntax;
109 PicParams_Avs2d *pp = &syntax->pp;
110 AlfParams_Avs2d *alfp = &syntax->alfp;
111 RefParams_Avs2d *refp = &syntax->refp;
112 WqmParams_Avs2d *wqmp = &syntax->wqmp;
113
114 memset(data, 0, len);
115
116 mpp_set_bitput_ctx(&bp, bit_buf, len);
117 //!< sequence header syntax
118 mpp_put_bits(&bp, pp->chroma_format_idc, 2);
119 mpp_put_bits(&bp, pp->pic_width_in_luma_samples, 16);
120 mpp_put_bits(&bp, pp->pic_height_in_luma_samples, 16);
121 mpp_put_bits(&bp, pp->bit_depth_luma_minus8, 3);
122 mpp_put_bits(&bp, pp->bit_depth_chroma_minus8, 3);
123 mpp_put_bits(&bp, pp->lcu_size, 3);
124 mpp_put_bits(&bp, pp->progressive_sequence, 1);
125 mpp_put_bits(&bp, pp->field_coded_sequence, 1);
126 mpp_put_bits(&bp, pp->multi_hypothesis_skip_enable_flag, 1);
127 mpp_put_bits(&bp, pp->dual_hypothesis_prediction_enable_flag, 1);
128 mpp_put_bits(&bp, pp->weighted_skip_enable_flag, 1);
129 mpp_put_bits(&bp, pp->asymmetrc_motion_partitions_enable_flag, 1);
130 mpp_put_bits(&bp, pp->nonsquare_quadtree_transform_enable_flag, 1);
131 mpp_put_bits(&bp, pp->nonsquare_intra_prediction_enable_flag, 1);
132 mpp_put_bits(&bp, pp->secondary_transform_enable_flag, 1);
133 mpp_put_bits(&bp, pp->sample_adaptive_offset_enable_flag, 1);
134 mpp_put_bits(&bp, pp->adaptive_loop_filter_enable_flag, 1);
135 mpp_put_bits(&bp, pp->pmvr_enable_flag, 1);
136 mpp_put_bits(&bp, pp->cross_slice_loopfilter_enable_flag, 1);
137 //!< picture header syntax
138 mpp_put_bits(&bp, pp->picture_type, 3);
139 mpp_put_bits(&bp, refp->ref_pic_num, 3);
140 mpp_put_bits(&bp, pp->scene_reference_enable_flag, 1);
141 mpp_put_bits(&bp, pp->bottom_field_picture_flag, 1);
142 mpp_put_bits(&bp, pp->fixed_picture_qp, 1);
143 mpp_put_bits(&bp, pp->picture_qp, 7);
144 mpp_put_bits(&bp, pp->loop_filter_disable_flag, 1);
145 mpp_put_bits(&bp, pp->alpha_c_offset, 5);
146 mpp_put_bits(&bp, pp->beta_offset, 5);
147 //!< weight quant param
148 mpp_put_bits(&bp, wqmp->chroma_quant_param_delta_cb, 6);
149 mpp_put_bits(&bp, wqmp->chroma_quant_param_delta_cr, 6);
150 mpp_put_bits(&bp, wqmp->pic_weight_quant_enable_flag, 1);
151 //!< alf param
152 mpp_put_bits(&bp, alfp->enable_pic_alf_y, 1);
153 mpp_put_bits(&bp, alfp->enable_pic_alf_cb, 1);
154 mpp_put_bits(&bp, alfp->enable_pic_alf_cr, 1);
155
156 if (alfp->enable_pic_alf_y) {
157 RK_U32 alf_filter_num = alfp->alf_filter_num_minus1 + 1;
158 mpp_put_bits(&bp, alfp->alf_filter_num_minus1, 4);
159
160 for (i = 0; i < 16; i++)
161 mpp_put_bits(&bp, alfp->alf_coeff_idx_tab[i], 4);
162
163 for (i = 0; i < alf_filter_num; i++) {
164 for (j = 0; j < 9; j++) {
165 mpp_put_bits(&bp, alfp->alf_coeff_y[i][j], 7);
166 }
167 }
168 }
169
170 if (alfp->enable_pic_alf_cb) {
171 for (j = 0; j < 9; j++)
172 mpp_put_bits(&bp, alfp->alf_coeff_cb[j], 7);
173 }
174
175 if (alfp->enable_pic_alf_cr) {
176 for (j = 0; j < 9; j++)
177 mpp_put_bits(&bp, alfp->alf_coeff_cr[j], 7);
178 }
179
180 mpp_put_align(&bp, 128, 0);
181
182 return MPP_OK;
183 }
184
prepare_scalist(Avs2dHalCtx_t * p_hal,RK_U8 * data,RK_U32 len)185 static MPP_RET prepare_scalist(Avs2dHalCtx_t *p_hal, RK_U8 *data, RK_U32 len)
186 {
187 RK_U32 i, j;
188 RK_U32 size_id, block_size;
189 BitputCtx_t bp;
190 RK_U64 *bit_buf = (RK_U64 *)data;
191 Avs2dSyntax_t *syntax = &p_hal->syntax;
192 WqmParams_Avs2d *wqmp = &syntax->wqmp;
193
194 if (!wqmp->pic_weight_quant_enable_flag)
195 return MPP_OK;
196
197 memset(data, 0, len);
198
199 mpp_set_bitput_ctx(&bp, bit_buf, len);
200
201 for (size_id = 0; size_id < 2; size_id++) {
202 block_size = MPP_MIN(1 << (size_id + 2), 8);
203 for (i = 0; i < block_size; i++) {
204 for (j = 0 ; j < block_size; j++)
205 //!< row col reversed
206 mpp_put_bits(&bp, wqmp->wq_matrix[size_id][size_id * j + i], 8);
207 }
208 }
209
210 return MPP_OK;
211 }
212
get_frame_fd(Avs2dHalCtx_t * p_hal,RK_S32 idx)213 static RK_S32 get_frame_fd(Avs2dHalCtx_t *p_hal, RK_S32 idx)
214 {
215 RK_S32 ret_fd = 0;
216 MppBuffer mbuffer = NULL;
217
218 mpp_buf_slot_get_prop(p_hal->frame_slots, idx, SLOT_BUFFER, &mbuffer);
219 ret_fd = mpp_buffer_get_fd(mbuffer);
220
221 return ret_fd;
222 }
223
get_packet_fd(Avs2dHalCtx_t * p_hal,RK_S32 idx)224 static RK_S32 get_packet_fd(Avs2dHalCtx_t *p_hal, RK_S32 idx)
225 {
226 RK_S32 ret_fd = 0;
227 MppBuffer mbuffer = NULL;
228
229 mpp_buf_slot_get_prop(p_hal->packet_slots, idx, SLOT_BUFFER, &mbuffer);
230 ret_fd = mpp_buffer_get_fd(mbuffer);
231
232 return ret_fd;
233 }
234
init_common_regs(Vdpu382Avs2dRegSet * regs)235 static MPP_RET init_common_regs(Vdpu382Avs2dRegSet *regs)
236 {
237 Vdpu382RegCommon *common = ®s->common;
238
239 common->reg009.dec_mode = 3; // AVS2
240 common->reg015.rlc_mode = 0;
241
242 common->reg011.buf_empty_en = 1;
243 common->reg011.err_head_fill_e = 1;
244 common->reg011.err_colmv_fill_e = 1;
245
246 common->reg010.dec_e = 1;
247
248 common->reg013.h26x_error_mode = 0;
249 common->reg021.inter_error_prc_mode = 0;
250 common->reg021.error_deb_en = 0;
251 common->reg021.error_intra_mode = 0;
252
253 common->reg024.cabac_err_en_lowbits = 0xffffffdf;
254 common->reg025.cabac_err_en_highbits = 0x3dffffff;
255
256 common->reg026.inter_auto_gating_e = 1;
257 common->reg026.filterd_auto_gating_e = 1;
258 common->reg026.strmd_auto_gating_e = 1;
259 common->reg026.mcp_auto_gating_e = 1;
260 common->reg026.busifd_auto_gating_e = 1;
261 common->reg026.dec_ctrl_auto_gating_e = 1;
262 common->reg026.intra_auto_gating_e = 1;
263 common->reg026.mc_auto_gating_e = 1;
264 common->reg026.transd_auto_gating_e = 1;
265 common->reg026.sram_auto_gating_e = 1;
266 common->reg026.cru_auto_gating_e = 1;
267 common->reg026.reg_cfg_gating_en = 1;
268
269 common->reg032_timeout_threshold = 0x3fffff;
270
271 common->reg011.dec_clkgate_e = 1;
272
273 common->reg013.stmerror_waitdecfifo_empty = 1;
274 common->reg012.colmv_compress_en = COLMV_COMPRESS_EN;
275 common->reg012.info_collect_en = 1;
276 common->reg012.error_info_en = 0;
277
278 return MPP_OK;
279 }
280
avs2d_refine_rcb_size(Vdpu382RcbInfo * rcb_info,Vdpu382Avs2dRegSet * hw_regs,RK_S32 width,RK_S32 height,void * dxva)281 static void avs2d_refine_rcb_size(Vdpu382RcbInfo *rcb_info,
282 Vdpu382Avs2dRegSet *hw_regs,
283 RK_S32 width, RK_S32 height, void *dxva)
284 {
285 (void) height;
286 Avs2dSyntax_t *syntax = dxva;
287 RK_U8 ctu_size = 1 << syntax->pp.lcu_size;
288 RK_U32 chroma_fmt_idc = syntax->pp.chroma_format_idc;
289 RK_U8 bit_depth = syntax->pp.bit_depth_chroma_minus8 + 8;
290 RK_U32 rcb_bits = 0;
291
292 width = MPP_ALIGN(width, ctu_size);
293
294 /* RCB_STRMD_ROW */
295 if (width >= 8192) {
296 RK_U32 factor = 64 / ctu_size;
297
298 rcb_bits = (MPP_ALIGN(width, ctu_size) + factor - 1) / factor * 24;
299 } else
300 rcb_bits = 0;
301 rcb_info[RCB_STRMD_ROW].size = MPP_RCB_BYTES(rcb_bits);
302
303 /* RCB_TRANSD_ROW */
304 if (width >= 8192)
305 rcb_bits = (MPP_ALIGN(width - 8192, 4) << 1);
306 else
307 rcb_bits = 0;
308 rcb_info[RCB_TRANSD_ROW].size = MPP_RCB_BYTES(rcb_bits);
309
310 /* RCB_TRANSD_COL */
311 rcb_info[RCB_TRANSD_COL].size = 0;
312
313 /* RCB_INTER_ROW */
314 rcb_bits = width * 21;
315 rcb_info[RCB_INTER_ROW].size = MPP_RCB_BYTES(rcb_bits);
316
317 /* RCB_INTER_COL */
318 rcb_info[RCB_INTER_COL].size = 0;
319
320 /* RCB_INTRA_ROW */
321 rcb_bits = width * ((chroma_fmt_idc ? 1 : 0) + 1) * 11;
322 rcb_info[RCB_INTRA_ROW].size = MPP_RCB_BYTES(rcb_bits);
323
324 /* RCB_DBLK_ROW */
325 if (chroma_fmt_idc == 1 ) {
326 if (ctu_size == 32)
327 rcb_bits = width * ( 4 + 8 * bit_depth);
328 else
329 rcb_bits = width * ( 2 + 8 * bit_depth);
330 } else
331 rcb_bits = 0;
332 rcb_info[RCB_DBLK_ROW].size = MPP_RCB_BYTES(rcb_bits);
333
334 /* RCB_SAO_ROW */
335 if (chroma_fmt_idc == 1 || chroma_fmt_idc == 2) {
336 rcb_bits = width * (128 / ctu_size + 2 * bit_depth);
337 } else {
338 rcb_bits = width * (128 / ctu_size + 3 * bit_depth);
339 }
340 rcb_info[RCB_SAO_ROW].size = MPP_RCB_BYTES(rcb_bits);
341
342 /* RCB_FBC_ROW */
343 if (hw_regs->common.reg012.fbc_e)
344 rcb_bits = width * 4 * bit_depth;
345 else
346 rcb_bits = 0;
347 rcb_info[RCB_FBC_ROW].size = MPP_RCB_BYTES(rcb_bits);
348
349 /* RCB_FILT_COL */
350 rcb_info[RCB_FILT_COL].size = 0;
351 return;
352 }
353
hal_avs2d_rcb_info_update(void * hal,Vdpu382Avs2dRegSet * hw_regs)354 static void hal_avs2d_rcb_info_update(void *hal, Vdpu382Avs2dRegSet *hw_regs)
355 {
356 MPP_RET ret = MPP_OK;
357 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
358 Avs2dVdpu382RegCtx_t *reg_ctx = (Avs2dVdpu382RegCtx_t *)p_hal->reg_ctx;
359 RK_S32 width = p_hal->syntax.pp.pic_width_in_luma_samples;
360 RK_S32 height = p_hal->syntax.pp.pic_height_in_luma_samples;
361 RK_S32 i = 0;
362 RK_S32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
363
364 reg_ctx->rcb_buf_size = vdpu382_get_rcb_buf_size(reg_ctx->rcb_info, width, height);
365 avs2d_refine_rcb_size(reg_ctx->rcb_info, hw_regs, width, height, (void *)&p_hal->syntax);
366
367 for (i = 0; i < loop; i++) {
368 MppBuffer rcb_buf = NULL;
369
370 if (reg_ctx->rcb_buf[i]) {
371 mpp_buffer_put(reg_ctx->rcb_buf[i]);
372 reg_ctx->rcb_buf[i] = NULL;
373 }
374
375 ret = mpp_buffer_get(p_hal->buf_group, &rcb_buf, reg_ctx->rcb_buf_size);
376
377 if (ret)
378 mpp_err_f("AVS2D mpp_buffer_group_get failed\n");
379
380 reg_ctx->rcb_buf[i] = rcb_buf;
381 }
382 }
383
fill_registers(Avs2dHalCtx_t * p_hal,Vdpu382Avs2dRegSet * p_regs,HalTaskInfo * task)384 static MPP_RET fill_registers(Avs2dHalCtx_t *p_hal, Vdpu382Avs2dRegSet *p_regs, HalTaskInfo *task)
385 {
386 MPP_RET ret = MPP_OK;
387 RK_U32 i;
388 MppFrame mframe = NULL;
389 Avs2dSyntax_t *syntax = &p_hal->syntax;
390 PicParams_Avs2d *pp = &syntax->pp;
391 RefParams_Avs2d *refp = &syntax->refp;
392 HalDecTask *task_dec = &task->dec;
393 Vdpu382RegCommon *common = &p_regs->common;
394 RK_U32 is_fbc = 0;
395 HalBuf *mv_buf = NULL;
396
397 mpp_buf_slot_get_prop(p_hal->frame_slots, task_dec->output, SLOT_FRAME_PTR, &mframe);
398 is_fbc = MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe));
399
400 //!< caculate the yuv_frame_size
401 {
402 RK_U32 hor_virstride = 0;
403 RK_U32 ver_virstride = 0;
404 RK_U32 y_virstride = 0;
405
406 hor_virstride = mpp_frame_get_hor_stride(mframe);
407 ver_virstride = mpp_frame_get_ver_stride(mframe);
408 y_virstride = hor_virstride * ver_virstride;
409 AVS2D_HAL_TRACE("is_fbc %d y_virstride %d, hor_virstride %d, ver_virstride %d\n", is_fbc, y_virstride, hor_virstride, ver_virstride);
410
411 if (is_fbc) {
412 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
413 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K);
414
415 common->reg012.fbc_e = 1;
416 common->reg018.y_hor_virstride = fbc_hdr_stride / 16;
417 common->reg019.uv_hor_virstride = fbc_hdr_stride / 16;
418 common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
419 } else {
420 common->reg012.fbc_e = 0;
421 common->reg018.y_hor_virstride = hor_virstride / 16;
422 common->reg019.uv_hor_virstride = hor_virstride / 16;
423 common->reg020_y_virstride.y_virstride = y_virstride / 16;
424 }
425 common->reg013.cur_pic_is_idr = (pp->picture_type == 0 || pp->picture_type == 4 || pp->picture_type == 5);
426 }
427
428 // set current
429 {
430 RK_S32 fd = -1;
431 p_regs->avs2d_param.reg65_cur_top_poc = mpp_frame_get_poc(mframe);
432 p_regs->avs2d_param.reg66_cur_bot_poc = 0;
433 fd = get_frame_fd(p_hal, task_dec->output);
434 mpp_assert(fd >= 0);
435 p_regs->common_addr.reg130_decout_base = fd;
436 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, task_dec->output);
437 p_regs->common_addr.reg131_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]);
438 AVS2D_HAL_TRACE("cur frame index %d, fd %d, colmv fd %d", task_dec->output, fd, p_regs->common_addr.reg131_colmv_cur_base);
439 }
440
441 // set reference
442 {
443 RK_U64 ref_flag = 0;
444 RK_S32 valid_slot = -1;
445 RK_U32 *ref_low = (RK_U32 *)&p_regs->avs2d_param.reg99;
446 RK_U32 *ref_hight = (RK_U32 *)&p_regs->avs2d_param.reg100;
447 RK_U32 err_ref_base = 0;
448
449 AVS2D_HAL_TRACE("num of ref %d", refp->ref_pic_num);
450
451 for (i = 0; i < refp->ref_pic_num; i++) {
452 if (task_dec->refer[i] < 0)
453 continue;
454
455 valid_slot = i;
456 break;
457 }
458
459 for (i = 0; i < refp->ref_pic_num; i++) {
460 MppFrame frame_ref = NULL;
461
462 RK_S32 slot_idx = task_dec->refer[i] < 0 ? task_dec->refer[valid_slot] : task_dec->refer[i];
463
464 if (slot_idx < 0) {
465 AVS2D_HAL_DBG(AVS2D_HAL_DBG_ERROR, "missing ref, could not found valid ref");
466 task->dec.flags.ref_err = 1;
467 return ret = MPP_ERR_UNKNOW;
468 }
469
470 mpp_buf_slot_get_prop(p_hal->frame_slots, slot_idx, SLOT_FRAME_PTR, &frame_ref);
471
472 if (frame_ref) {
473 RK_U32 frm_flag = 1 << 3;
474
475 if (pp->bottom_field_picture_flag)
476 frm_flag |= 1 << 2;
477
478 if (pp->field_coded_sequence)
479 frm_flag |= 1;
480
481 ref_flag |= frm_flag << (i * 8);
482
483 p_regs->avs2d_addr.ref_base[i] = get_frame_fd(p_hal, slot_idx);
484 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, slot_idx);
485 p_regs->avs2d_addr.colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
486
487 p_regs->avs2d_param.reg67_098_ref_poc[i] = mpp_frame_get_poc(frame_ref);
488 if (!err_ref_base && !mpp_frame_get_errinfo(frame_ref))
489 err_ref_base = p_regs->avs2d_addr.ref_base[i];
490
491 AVS2D_HAL_TRACE("ref_base[%d] index=%d, fd = %d, colmv %d, poc %d",
492 i, slot_idx, p_regs->avs2d_addr.ref_base[i],
493 p_regs->avs2d_addr.colmv_base[i], p_regs->avs2d_param.reg67_098_ref_poc[i]);
494 }
495 }
496
497 if (p_hal->syntax.refp.scene_ref_enable && p_hal->syntax.refp.scene_ref_slot_idx >= 0) {
498 MppFrame scene_ref = NULL;
499 RK_S32 replace_idx = p_hal->syntax.refp.scene_ref_replace_pos;
500 RK_S32 slot_idx = p_hal->syntax.refp.scene_ref_slot_idx;
501
502 mpp_buf_slot_get_prop(p_hal->frame_slots, slot_idx, SLOT_FRAME_PTR, &scene_ref);
503
504 if (scene_ref) {
505 p_regs->avs2d_addr.ref_base[replace_idx] = get_frame_fd(p_hal, slot_idx);
506 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, slot_idx);
507 p_regs->avs2d_addr.colmv_base[replace_idx] = mpp_buffer_get_fd(mv_buf->buf[0]);
508 p_regs->avs2d_param.reg67_098_ref_poc[replace_idx] = mpp_frame_get_poc(scene_ref);
509 }
510 }
511
512 *ref_low = (RK_U32) (ref_flag & 0xffffffff);
513 *ref_hight = (RK_U32) ((ref_flag >> 32) & 0xffffffff);
514
515 p_regs->common_addr.reg132_error_ref_base = err_ref_base;
516 }
517
518 // set rlc
519 {
520 p_regs->common_addr.reg128_rlc_base = get_packet_fd(p_hal, task_dec->input);
521 AVS2D_HAL_TRACE("packet fd %d from slot %d", p_regs->common_addr.reg128_rlc_base, task_dec->input);
522 p_regs->common_addr.reg129_rlcwrite_base = p_regs->common_addr.reg128_rlc_base;
523 common->reg016_str_len = MPP_ALIGN(mpp_packet_get_length(task_dec->input_packet), 16) + 64;
524 }
525
526 /* set scale down info */
527 if (mpp_frame_get_thumbnail_en(mframe)) {
528 p_regs->avs2d_addr.scale_down_luma_base = p_regs->common_addr.reg130_decout_base;
529 p_regs->avs2d_addr.scale_down_chorme_base = p_regs->common_addr.reg130_decout_base;
530 vdpu382_setup_down_scale(mframe, p_hal->dev, &p_regs->common);
531 } else {
532 p_regs->avs2d_addr.scale_down_luma_base = 0;
533 p_regs->avs2d_addr.scale_down_chorme_base = 0;
534 p_regs->common.reg012.scale_down_en = 0;
535 }
536
537 return ret;
538 }
539
hal_avs2d_vdpu382_deinit(void * hal)540 MPP_RET hal_avs2d_vdpu382_deinit(void *hal)
541 {
542 MPP_RET ret = MPP_OK;
543 RK_U32 i, loop;
544 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
545 Avs2dVdpu382RegCtx_t *reg_ctx = (Avs2dVdpu382RegCtx_t *)p_hal->reg_ctx;
546
547 AVS2D_HAL_TRACE("In.");
548
549 INP_CHECK(ret, NULL == reg_ctx);
550
551 //!< malloc buffers
552 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
553 for (i = 0; i < loop; i++) {
554 if (reg_ctx->rcb_buf[i]) {
555 mpp_buffer_put(reg_ctx->rcb_buf[i]);
556 reg_ctx->rcb_buf[i] = NULL;
557 }
558
559 MPP_FREE(reg_ctx->reg_buf[i].regs);
560 }
561
562 if (reg_ctx->bufs) {
563 mpp_buffer_put(reg_ctx->bufs);
564 reg_ctx->bufs = NULL;
565 }
566
567 if (p_hal->cmv_bufs) {
568 hal_bufs_deinit(p_hal->cmv_bufs);
569 p_hal->cmv_bufs = NULL;
570 }
571
572 MPP_FREE(p_hal->reg_ctx);
573
574 __RETURN:
575 AVS2D_HAL_TRACE("Out. ret %d", ret);
576 return ret;
577 }
578
hal_avs2d_vdpu382_init(void * hal,MppHalCfg * cfg)579 MPP_RET hal_avs2d_vdpu382_init(void *hal, MppHalCfg *cfg)
580 {
581 MPP_RET ret = MPP_OK;
582 RK_U32 i, loop;
583 Avs2dVdpu382RegCtx_t *reg_ctx;
584 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
585
586 AVS2D_HAL_TRACE("In.");
587
588 INP_CHECK(ret, NULL == p_hal);
589
590 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Avs2dVdpu382RegCtx_t)));
591 reg_ctx = (Avs2dVdpu382RegCtx_t *)p_hal->reg_ctx;
592
593 //!< malloc buffers
594 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
595 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, ®_ctx->bufs, AVS2_ALL_TBL_BUF_SIZE(loop)));
596 reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs);
597 reg_ctx->bufs_ptr = mpp_buffer_get_ptr(reg_ctx->bufs);
598
599 for (i = 0; i < loop; i++) {
600 reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu382Avs2dRegSet, 1);
601 init_common_regs(reg_ctx->reg_buf[i].regs);
602 reg_ctx->reg_buf[i].offset_shph = AVS2_SHPH_OFFSET(i);
603 reg_ctx->reg_buf[i].offset_sclst = AVS2_SCALIST_OFFSET(i);
604 }
605
606 if (!p_hal->fast_mode) {
607 reg_ctx->regs = reg_ctx->reg_buf[0].regs;
608 reg_ctx->shph_offset = reg_ctx->reg_buf[0].offset_shph;
609 reg_ctx->sclst_offset = reg_ctx->reg_buf[0].offset_sclst;
610 }
611
612 if (MPP_FRAME_FMT_IS_FBC(cfg->cfg->base.out_fmt))
613 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, avs2d_hor_align_64);
614 else
615 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, avs2d_hor_align);
616
617 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, avs2d_hor_align);
618 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, avs2d_ver_align);
619 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, avs2d_len_align);
620
621 __RETURN:
622 AVS2D_HAL_TRACE("Out. ret %d", ret);
623 (void)cfg;
624 return ret;
625 __FAILED:
626 hal_avs2d_vdpu382_deinit(p_hal);
627 AVS2D_HAL_TRACE("Out. ret %d", ret);
628 return ret;
629 }
630
set_up_colmv_buf(void * hal)631 static MPP_RET set_up_colmv_buf(void *hal)
632 {
633 MPP_RET ret = MPP_OK;
634 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
635 Avs2dSyntax_t *syntax = &p_hal->syntax;
636 PicParams_Avs2d *pp = &syntax->pp;
637 RK_U32 mv_size = 0;
638 RK_U32 ctu_size = 1 << (p_hal->syntax.pp.lcu_size);
639 RK_U32 width = p_hal->syntax.pp.pic_width_in_luma_samples;
640 RK_U32 height = p_hal->syntax.pp.pic_height_in_luma_samples;
641
642 mv_size = vdpu382_get_colmv_size(width, height, ctu_size, COLMV_BYTES,
643 COLMV_BLOCK_SIZE, COLMV_COMPRESS_EN);
644 if (pp->field_coded_sequence)
645 mv_size *= 2;
646 AVS2D_HAL_TRACE("mv_size %d", mv_size);
647
648 if (p_hal->cmv_bufs == NULL || p_hal->mv_size < mv_size) {
649 size_t size = mv_size;
650
651 if (p_hal->cmv_bufs) {
652 hal_bufs_deinit(p_hal->cmv_bufs);
653 p_hal->cmv_bufs = NULL;
654 }
655
656 hal_bufs_init(&p_hal->cmv_bufs);
657 if (p_hal->cmv_bufs == NULL) {
658 mpp_err_f("colmv bufs init fail");
659 ret = MPP_ERR_INIT;
660 goto __RETURN;
661 }
662
663 p_hal->mv_size = mv_size;
664 p_hal->mv_count = mpp_buf_slot_get_count(p_hal->frame_slots);
665 hal_bufs_setup(p_hal->cmv_bufs, p_hal->mv_count, 1, &size);
666 }
667
668 __RETURN:
669 return ret;
670 }
671
hal_avs2d_vdpu382_gen_regs(void * hal,HalTaskInfo * task)672 MPP_RET hal_avs2d_vdpu382_gen_regs(void *hal, HalTaskInfo *task)
673 {
674 MPP_RET ret = MPP_OK;
675 Avs2dVdpu382RegCtx_t *reg_ctx;
676 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
677 Vdpu382Avs2dRegSet *regs = NULL;
678
679 AVS2D_HAL_TRACE("In.");
680
681 INP_CHECK(ret, NULL == p_hal);
682
683 if ((task->dec.flags.parse_err || task->dec.flags.ref_err) &&
684 !p_hal->cfg->base.disable_error) {
685 ret = MPP_NOK;
686 goto __RETURN;
687 }
688
689 ret = set_up_colmv_buf(p_hal);
690 if (ret)
691 goto __RETURN;
692
693 reg_ctx = (Avs2dVdpu382RegCtx_t *)p_hal->reg_ctx;
694
695 if (p_hal->fast_mode) {
696 RK_U32 i = 0;
697
698 for (i = 0; i < MPP_ARRAY_ELEMS(reg_ctx->reg_buf); i++) {
699 if (!reg_ctx->reg_buf[i].valid) {
700 task->dec.reg_index = i;
701 regs = reg_ctx->reg_buf[i].regs;
702 reg_ctx->shph_offset = reg_ctx->reg_buf[i].offset_shph;
703 reg_ctx->sclst_offset = reg_ctx->reg_buf[i].offset_sclst;
704 reg_ctx->regs = reg_ctx->reg_buf[i].regs;
705 reg_ctx->reg_buf[i].valid = 1;
706 break;
707 }
708 }
709
710 mpp_assert(regs);
711 }
712
713 regs = reg_ctx->regs;
714
715 prepare_header(p_hal, reg_ctx->shph_dat, sizeof(reg_ctx->shph_dat));
716 prepare_scalist(p_hal, reg_ctx->scalist_dat, sizeof(reg_ctx->scalist_dat));
717
718 ret = fill_registers(p_hal, regs, task);
719
720 if (ret)
721 goto __RETURN;
722
723 {
724 memcpy(reg_ctx->bufs_ptr + reg_ctx->shph_offset, reg_ctx->shph_dat, sizeof(reg_ctx->shph_dat));
725 memcpy(reg_ctx->bufs_ptr + reg_ctx->sclst_offset, reg_ctx->scalist_dat, sizeof(reg_ctx->scalist_dat));
726 regs->common.reg012.scanlist_addr_valid_en = 1;
727
728 regs->avs2d_addr.head_base = reg_ctx->bufs_fd;
729 mpp_dev_set_reg_offset(p_hal->dev, 161, reg_ctx->shph_offset);
730
731 regs->avs2d_param.reg105.head_len = AVS2_RKV_SHPH_SIZE / 16;
732 regs->avs2d_param.reg105.head_len -= (regs->avs2d_param.reg105.head_len > 0) ? 1 : 0;
733
734 regs->avs2d_addr.scanlist_addr = reg_ctx->bufs_fd;
735 mpp_dev_set_reg_offset(p_hal->dev, 180, reg_ctx->sclst_offset);
736 }
737
738 if (avs2d_hal_debug & AVS2D_HAL_DBG_IN) {
739 FILE *fp_shph = NULL;
740 char name[50];
741 snprintf(name, sizeof(name), "/data/tmp/rkv_shph_%03d.bin", p_hal->frame_no);
742 fp_shph = fopen(name, "wb");
743 fwrite(reg_ctx->bufs_ptr + reg_ctx->shph_offset, 1, sizeof(reg_ctx->shph_dat), fp_shph);
744 fclose(fp_shph);
745 }
746
747 if (avs2d_hal_debug & AVS2D_HAL_DBG_IN) {
748 FILE *fp_scalist = NULL;
749 char name[50];
750 snprintf(name, sizeof(name), "/data/tmp/rkv_scalist_%03d.bin", p_hal->frame_no);
751 fp_scalist = fopen(name, "wb");
752 fwrite(reg_ctx->bufs_ptr + reg_ctx->sclst_offset, 1, sizeof(reg_ctx->scalist_dat), fp_scalist);
753 fclose(fp_scalist);
754 }
755
756 // set rcb
757 {
758 hal_avs2d_rcb_info_update(p_hal, regs);
759 vdpu382_setup_rcb(®s->common_addr, p_hal->dev, p_hal->fast_mode ?
760 reg_ctx->rcb_buf[task->dec.reg_index] : reg_ctx->rcb_buf[0],
761 reg_ctx->rcb_info);
762
763 }
764
765 if (avs2d_hal_debug & AVS2D_HAL_DBG_IN) {
766 FILE *fp_rcb = NULL;
767 char name[50];
768 void *base = NULL;
769 snprintf(name, sizeof(name), "/data/tmp/rkv_rcb_%03d.bin", p_hal->frame_no);
770 fp_rcb = fopen(name, "wb");
771 base = mpp_buffer_get_ptr(reg_ctx->rcb_buf[0]);
772 fwrite(base, 1, reg_ctx->rcb_buf_size, fp_rcb);
773 fclose(fp_rcb);
774
775 }
776
777 vdpu382_setup_statistic(®s->common, ®s->statistic);
778 mpp_buffer_sync_end(reg_ctx->bufs);
779
780 /* enable reference frame usage feedback */
781 regs->statistic.reg265.perf_cnt0_sel = 42;
782
783 __RETURN:
784 AVS2D_HAL_TRACE("Out. ret %d", ret);
785 return ret;
786 }
787
hal_avs2d_vdpu382_dump_reg_write(void * hal,Vdpu382Avs2dRegSet * regs)788 static MPP_RET hal_avs2d_vdpu382_dump_reg_write(void *hal, Vdpu382Avs2dRegSet *regs)
789 {
790 MPP_RET ret = MPP_OK;
791 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
792 FILE *fp_reg = NULL;
793 RK_U32 i = 0;
794 char name[50];
795 snprintf(name, sizeof(name), "/data/tmp/rkv_reg_write_%03d.txt", p_hal->frame_no);
796 fp_reg = fopen(name , "w+");
797
798 fprintf(fp_reg, "********Frame num %d\n", p_hal->frame_no);
799 for (i = 0; i < 8; i++)
800 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i, 0);
801
802 for (i = 0; i < sizeof(Vdpu382RegCommon) / sizeof(RK_U32); i++)
803 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_COMMON_REGS / sizeof(RK_U32)),
804 ((RK_U32 *)®s->common)[i]);
805
806 for (i = 0; i < 63 - 32; i++)
807 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i + 33, 0);
808
809 for (i = 0; i < sizeof(Vdpu382RegAvs2dParam) / sizeof(RK_U32); i++)
810 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_CODEC_PARAMS_REGS / sizeof(RK_U32)),
811 ((RK_U32 *)®s->avs2d_param)[i]);
812
813 for (i = 0; i < 127 - 112; i++)
814 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i + 113, 0);
815
816 for (i = 0; i < sizeof(Vdpu382RegCommonAddr) / sizeof(RK_U32); i++)
817 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_COMMON_ADDR_REGS / sizeof(RK_U32)),
818 ((RK_U32 *)®s->common_addr)[i]);
819
820 for (i = 0; i < 159 - 142; i++)
821 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i + 143, 0);
822
823
824 for (i = 0; i < sizeof(Vdpu382RegAvs2dAddr) / sizeof(RK_U32); i++ )
825 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_CODEC_ADDR_REGS / sizeof(RK_U32)),
826 ((RK_U32 *)®s->avs2d_addr)[i]);
827
828 for (i = 0; i < 223 - 197; i++)
829 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i + 198, 0);
830
831 for (i = 0; i < sizeof(Vdpu382RegIrqStatus) / sizeof(RK_U32); i++ )
832 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_INTERRUPT_REGS / sizeof(RK_U32)),
833 ((RK_U32 *)®s->irq_status)[i]);
834
835 for (i = 0; i < 255 - 237; i++)
836 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i + 238, 0);
837
838 for (i = 0; i < sizeof(Vdpu382RegStatistic) / sizeof(RK_U32); i++ )
839 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_STATISTIC_REGS / sizeof(RK_U32)),
840 ((RK_U32 *)®s->statistic)[i]);
841
842 fclose(fp_reg);
843 return ret;
844 }
845
hal_avs2d_vdpu382_dump_stream(void * hal,HalTaskInfo * task)846 static MPP_RET hal_avs2d_vdpu382_dump_stream(void *hal, HalTaskInfo *task)
847 {
848 MPP_RET ret = MPP_OK;
849 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
850
851 FILE *fp_stream = NULL;
852 char name[50];
853 MppBuffer buffer = NULL;
854 void *base = NULL;
855 mpp_buf_slot_get_prop(p_hal->packet_slots, task->dec.input, SLOT_BUFFER, &buffer);
856 base = mpp_buffer_get_ptr(buffer);
857 snprintf(name, sizeof(name), "/data/tmp/rkv_stream_in_%03d.bin", p_hal->frame_no);
858 fp_stream = fopen(name, "wb");
859 fwrite(base, 1, mpp_packet_get_length(task->dec.input_packet), fp_stream);
860 fclose(fp_stream);
861
862 return ret;
863 }
864
hal_avs2d_vdpu382_start(void * hal,HalTaskInfo * task)865 MPP_RET hal_avs2d_vdpu382_start(void *hal, HalTaskInfo *task)
866 {
867 MPP_RET ret = MPP_OK;
868 Vdpu382Avs2dRegSet *regs = NULL;
869 Avs2dVdpu382RegCtx_t *reg_ctx;
870 MppDev dev = NULL;
871 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
872
873 AVS2D_HAL_TRACE("In.");
874 INP_CHECK(ret, NULL == p_hal);
875
876 if ((task->dec.flags.parse_err || task->dec.flags.ref_err) &&
877 !p_hal->cfg->base.disable_error) {
878 ret = MPP_NOK;
879 goto __RETURN;
880 }
881
882 reg_ctx = (Avs2dVdpu382RegCtx_t *)p_hal->reg_ctx;
883 regs = p_hal->fast_mode ? reg_ctx->reg_buf[task->dec.reg_index].regs : reg_ctx->regs;
884 dev = p_hal->dev;
885
886 p_hal->frame_no++;
887
888 do {
889 MppDevRegWrCfg wr_cfg;
890 MppDevRegRdCfg rd_cfg;
891
892 wr_cfg.reg = ®s->common;
893 wr_cfg.size = sizeof(regs->common);
894 wr_cfg.offset = OFFSET_COMMON_REGS;
895
896 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
897
898 if (ret) {
899 mpp_err_f("set register write failed %d\n", ret);
900 break;
901 }
902
903 wr_cfg.reg = ®s->avs2d_param;
904 wr_cfg.size = sizeof(regs->avs2d_param);
905 wr_cfg.offset = OFFSET_CODEC_PARAMS_REGS;
906
907 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
908
909 if (ret) {
910 mpp_err_f("set register write failed %d\n", ret);
911 break;
912 }
913
914 wr_cfg.reg = ®s->common_addr;
915 wr_cfg.size = sizeof(regs->common_addr);
916 wr_cfg.offset = OFFSET_COMMON_ADDR_REGS;
917
918 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
919
920 if (ret) {
921 mpp_err_f("set register write failed %d\n", ret);
922 break;
923 }
924
925 wr_cfg.reg = ®s->avs2d_addr;
926 wr_cfg.size = sizeof(regs->avs2d_addr);
927 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS;
928
929 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
930
931 if (ret) {
932 mpp_err_f("set register write failed %d\n", ret);
933 break;
934 }
935
936 wr_cfg.reg = ®s->statistic;
937 wr_cfg.size = sizeof(regs->statistic);
938 wr_cfg.offset = OFFSET_STATISTIC_REGS;
939 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
940
941 if (ret) {
942 mpp_err_f("set register write failed %d\n", ret);
943 break;
944 }
945
946 rd_cfg.reg = ®s->irq_status;
947 rd_cfg.size = sizeof(regs->irq_status);
948 rd_cfg.offset = OFFSET_INTERRUPT_REGS;
949 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
950
951 if (ret) {
952 mpp_err_f("set register read failed %d\n", ret);
953 break;
954 }
955
956 rd_cfg.reg = ®s->avs2d_param;
957 rd_cfg.size = sizeof(regs->avs2d_param);
958 rd_cfg.offset = OFFSET_CODEC_PARAMS_REGS;
959 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
960
961 if (ret) {
962 mpp_err_f("set register read failed %d\n", ret);
963 break;
964 }
965
966 rd_cfg.reg = ®s->statistic;
967 rd_cfg.size = sizeof(regs->statistic);
968 rd_cfg.offset = OFFSET_STATISTIC_REGS;
969 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
970
971 if (ret) {
972 mpp_err_f("set register write failed %d\n", ret);
973 break;
974 }
975
976 if (avs2d_hal_debug & AVS2D_HAL_DBG_REG) {
977 memset(reg_ctx->reg_out, 0, sizeof(reg_ctx->reg_out));
978 rd_cfg.reg = reg_ctx->reg_out;
979 rd_cfg.size = sizeof(reg_ctx->reg_out);
980 rd_cfg.offset = 0;
981 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
982 }
983
984 // rcb info for sram
985 vdpu382_set_rcbinfo(dev, reg_ctx->rcb_info);
986
987 if (avs2d_hal_debug & AVS2D_HAL_DBG_IN)
988 hal_avs2d_vdpu382_dump_stream(hal, task);
989
990 if (avs2d_hal_debug & AVS2D_HAL_DBG_REG)
991 hal_avs2d_vdpu382_dump_reg_write(hal, regs);
992
993 // send request to hardware
994 ret = mpp_dev_ioctl(dev, MPP_DEV_CMD_SEND, NULL);
995 if (ret) {
996 mpp_err_f("send cmd failed %d\n", ret);
997 break;
998 }
999
1000 } while (0);
1001
1002 __RETURN:
1003 AVS2D_HAL_TRACE("Out.");
1004 return ret;
1005 }
1006
1007
fetch_data(RK_U32 fmt,RK_U8 * line,RK_U32 num)1008 static RK_U8 fetch_data(RK_U32 fmt, RK_U8 *line, RK_U32 num)
1009 {
1010 RK_U32 offset = 0;
1011 RK_U32 value = 0;
1012
1013 if (fmt == MPP_FMT_YUV420SP_10BIT) {
1014 offset = (num * 2) & 7;
1015 value = (line[num * 10 / 8] >> offset) |
1016 (line[num * 10 / 8 + 1] << (8 - offset));
1017
1018 value = (value & 0x3ff) >> 2;
1019 } else if (fmt == MPP_FMT_YUV420SP) {
1020 value = line[num];
1021 }
1022
1023 return value;
1024 }
1025
hal_avs2d_vdpu382_dump_yuv(void * hal,HalTaskInfo * task)1026 static MPP_RET hal_avs2d_vdpu382_dump_yuv(void *hal, HalTaskInfo *task)
1027 {
1028 MPP_RET ret = MPP_OK;
1029 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
1030
1031 MppFrameFormat fmt = MPP_FMT_YUV420SP;
1032 RK_U32 vir_w = 0;
1033 RK_U32 vir_h = 0;
1034 RK_U32 i = 0;
1035 RK_U32 j = 0;
1036 FILE *fp_stream = NULL;
1037 char name[50];
1038 MppBuffer buffer = NULL;
1039 MppFrame frame;
1040 void *base = NULL;
1041
1042 ret = mpp_buf_slot_get_prop(p_hal->frame_slots, task->dec.output, SLOT_FRAME_PTR, &frame);
1043
1044 if (ret != MPP_OK || frame == NULL)
1045 mpp_log_f("failed to get frame slot %d", task->dec.output);
1046
1047 ret = mpp_buf_slot_get_prop(p_hal->frame_slots, task->dec.output, SLOT_BUFFER, &buffer);
1048
1049 if (ret != MPP_OK || buffer == NULL)
1050 mpp_log_f("failed to get frame buffer slot %d", task->dec.output);
1051
1052 AVS2D_HAL_TRACE("frame slot %d, fd %d\n", task->dec.output, mpp_buffer_get_fd(buffer));
1053 base = mpp_buffer_get_ptr(buffer);
1054 vir_w = mpp_frame_get_hor_stride(frame);
1055 vir_h = mpp_frame_get_ver_stride(frame);
1056 fmt = mpp_frame_get_fmt(frame);
1057 snprintf(name, sizeof(name), "/data/tmp/rkv_out_%dx%d_nv12_%03d.yuv", vir_w, vir_h,
1058 p_hal->frame_no);
1059 fp_stream = fopen(name, "wb");
1060 /* if format is fbc, write fbc header first */
1061 if (MPP_FRAME_FMT_IS_FBC(fmt)) {
1062 RK_U32 header_size = 0;
1063
1064 header_size = vir_w * vir_h / 16;
1065 fwrite(base, 1, header_size, fp_stream);
1066 base += header_size;
1067 }
1068
1069 if (fmt != MPP_FMT_YUV420SP_10BIT) {
1070 fwrite(base, 1, vir_w * vir_h * 3 / 2, fp_stream);
1071 } else {
1072 RK_U8 tmp = 0;
1073 for (i = 0; i < vir_h; i++) {
1074 for (j = 0; j < vir_w; j++) {
1075 tmp = fetch_data(fmt, base, j);
1076 fwrite(&tmp, 1, 1, fp_stream);
1077 }
1078 base += vir_w;
1079 }
1080
1081 for (i = 0; i < vir_h / 2; i++) {
1082 for (j = 0; j < vir_w; j++) {
1083 tmp = fetch_data(fmt, base, j);
1084 fwrite(&tmp, 1, 1, fp_stream);
1085 }
1086 base += vir_w;
1087 }
1088 }
1089 fclose(fp_stream);
1090
1091 return ret;
1092 }
1093
hal_avs2d_vdpu382_wait(void * hal,HalTaskInfo * task)1094 MPP_RET hal_avs2d_vdpu382_wait(void *hal, HalTaskInfo *task)
1095 {
1096 MPP_RET ret = MPP_OK;
1097 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
1098 Avs2dVdpu382RegCtx_t *reg_ctx;
1099 Vdpu382Avs2dRegSet *p_regs;
1100
1101 INP_CHECK(ret, NULL == p_hal);
1102 reg_ctx = (Avs2dVdpu382RegCtx_t *)p_hal->reg_ctx;
1103 p_regs = p_hal->fast_mode ? reg_ctx->reg_buf[task->dec.reg_index].regs : reg_ctx->regs;
1104
1105 if ((task->dec.flags.parse_err || task->dec.flags.ref_err) &&
1106 !p_hal->cfg->base.disable_error) {
1107 AVS2D_HAL_DBG(AVS2D_HAL_DBG_ERROR, "found task error.\n");
1108 ret = MPP_NOK;
1109 goto __RETURN;
1110 } else {
1111 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL);
1112 if (ret)
1113 mpp_err_f("poll cmd failed %d\n", ret);
1114 }
1115
1116 if (avs2d_hal_debug & AVS2D_HAL_DBG_OUT)
1117 hal_avs2d_vdpu382_dump_yuv(hal, task);
1118
1119 if (avs2d_hal_debug & AVS2D_HAL_DBG_REG) {
1120 FILE *fp_reg = NULL;
1121 RK_U32 i = 0;
1122 char name[50];
1123 snprintf(name, sizeof(name), "/data/tmp/rkv_reg_read_%03d.txt", p_hal->frame_no);
1124 fp_reg = fopen(name , "w+");
1125
1126 for (i = 0; i < 278; i++)
1127 fprintf(fp_reg, "%08x\n", reg_ctx->reg_out[i]);
1128
1129 fclose(fp_reg);
1130 }
1131
1132 AVS2D_HAL_TRACE("read reg[224] 0x%08x\n", p_regs->irq_status.reg224);
1133
1134 if (p_hal->dec_cb) {
1135 DecCbHalDone param;
1136
1137 param.task = (void *)&task->dec;
1138 param.regs = (RK_U32 *)p_regs;
1139
1140 if (p_regs->irq_status.reg224.dec_error_sta ||
1141 (!p_regs->irq_status.reg224.dec_rdy_sta) ||
1142 p_regs->irq_status.reg224.buf_empty_sta ||
1143 p_regs->irq_status.reg226.strmd_error_status ||
1144 p_regs->irq_status.reg227.colmv_error_ref_picidx ||
1145 p_regs->irq_status.reg226.strmd_detect_error_flag)
1146 param.hard_err = 1;
1147 else
1148 param.hard_err = 0;
1149
1150 task->dec.flags.ref_used = p_regs->statistic.reg265.link_perf_cnt0;
1151 task->dec.flags.ref_info_valid = 1;
1152
1153 if (task->dec.flags.ref_miss) {
1154 RK_U32 ref_hw_usage = p_regs->statistic.reg265.link_perf_cnt0;
1155
1156 AVS2D_HAL_TRACE("hal frame %d ref miss %x hard_err %d hw_usage %x", p_hal->frame_no,
1157 task->dec.flags.ref_miss, param.hard_err, ref_hw_usage);
1158 }
1159
1160 AVS2D_HAL_TRACE("hal frame %d hard_err= %d", p_hal->frame_no, param.hard_err);
1161
1162 mpp_callback(p_hal->dec_cb, ¶m);
1163 }
1164
1165 memset(&p_regs->irq_status.reg224, 0, sizeof(RK_U32));
1166
1167 if (p_hal->fast_mode)
1168 reg_ctx->reg_buf[task->dec.reg_index].valid = 0;
1169
1170 __RETURN:
1171 AVS2D_HAL_TRACE("Out. ret %d", ret);
1172 return ret;
1173 }
1174
1175 const MppHalApi hal_avs2d_vdpu382 = {
1176 .name = "avs2d_vdpu382",
1177 .type = MPP_CTX_DEC,
1178 .coding = MPP_VIDEO_CodingAVS2,
1179 .ctx_size = sizeof(Avs2dVdpu382RegCtx_t),
1180 .flag = 0,
1181 .init = hal_avs2d_vdpu382_init,
1182 .deinit = hal_avs2d_vdpu382_deinit,
1183 .reg_gen = hal_avs2d_vdpu382_gen_regs,
1184 .start = hal_avs2d_vdpu382_start,
1185 .wait = hal_avs2d_vdpu382_wait,
1186 .reset = NULL,
1187 .flush = NULL,
1188 .control = NULL,
1189 };
1190