653         Vdpu34xH264dRegCtx *reg_ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx;  in set_registers()  local
659         regs->h264d_addr.cabactbl_base = reg_ctx->bufs_fd;  in set_registers()
660         mpp_dev_set_reg_offset(p_hal->dev, 197, reg_ctx->offset_cabac);  in set_registers()
715     MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Vdpu34xH264dRegCtx)));  in vdpu34x_h264d_init()
716     Vdpu34xH264dRegCtx *reg_ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx;  in vdpu34x_h264d_init()  local
721     FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, &reg_ctx->bufs,  in vdpu34x_h264d_init()
723     reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs);  in vdpu34x_h264d_init()
724     reg_ctx->bufs_ptr = mpp_buffer_get_ptr(reg_ctx->bufs);  in vdpu34x_h264d_init()
725     reg_ctx->offset_cabac = VDPU34X_CABAC_TAB_OFFSET;  in vdpu34x_h264d_init()
726     reg_ctx->offset_errinfo = VDPU34X_ERROR_INFO_OFFSET;  in vdpu34x_h264d_init()
728         reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu34xH264dRegSet, 1);  in vdpu34x_h264d_init()
729         init_common_regs(reg_ctx->reg_buf[i].regs);  in vdpu34x_h264d_init()
730         reg_ctx->offset_spspps[i] = VDPU34X_SPSPPS_OFFSET(i);  in vdpu34x_h264d_init()
731         reg_ctx->offset_rps[i] = VDPU34X_RPS_OFFSET(i);  in vdpu34x_h264d_init()
732         reg_ctx->offset_sclst[i] = VDPU34X_SCALING_LIST_OFFSET(i);  in vdpu34x_h264d_init()
736         reg_ctx->regs = reg_ctx->reg_buf[0].regs;  in vdpu34x_h264d_init()
737         reg_ctx->spspps_offset = reg_ctx->offset_spspps[0];  in vdpu34x_h264d_init()
738         reg_ctx->rps_offset = reg_ctx->offset_rps[0];  in vdpu34x_h264d_init()
739         reg_ctx->sclst_offset = reg_ctx->offset_sclst[0];  in vdpu34x_h264d_init()
743     memcpy((char *)reg_ctx->bufs_ptr + reg_ctx->offset_cabac,  in vdpu34x_h264d_init()
766     Vdpu34xH264dRegCtx *reg_ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx;  in vdpu34x_h264d_deinit()  local
769     RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;  in vdpu34x_h264d_deinit()
771     mpp_buffer_put(reg_ctx->bufs);  in vdpu34x_h264d_deinit()
774         MPP_FREE(reg_ctx->reg_buf[i].regs);  in vdpu34x_h264d_deinit()
776     loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->rcb_buf) : 1;  in vdpu34x_h264d_deinit()
778         if (reg_ctx->rcb_buf[i]) {  in vdpu34x_h264d_deinit()
779             mpp_buffer_put(reg_ctx->rcb_buf[i]);  in vdpu34x_h264d_deinit()
780             reg_ctx->rcb_buf[i] = NULL;  in vdpu34x_h264d_deinit()
789     MPP_FREE(p_hal->reg_ctx);  in vdpu34x_h264d_deinit()
852     Vdpu34xH264dRegCtx *ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx;  in hal_h264d_rcb_info_update()
928     Vdpu34xH264dRegCtx *ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx;  in vdpu34x_h264d_gen_regs()
1015     Vdpu34xH264dRegCtx *reg_ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx;  in vdpu34x_h264d_start()  local
1017                                reg_ctx->reg_buf[task->dec.reg_index].regs :  in vdpu34x_h264d_start()
1018                                reg_ctx->regs;  in vdpu34x_h264d_start()
1097         vdpu34x_set_rcbinfo(dev, reg_ctx->rcb_info);  in vdpu34x_h264d_start()
1117     Vdpu34xH264dRegCtx *reg_ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx;  in vdpu34x_h264d_wait()  local
1119                                  reg_ctx->reg_buf[task->dec.reg_index].regs :  in vdpu34x_h264d_wait()
1120                                  reg_ctx->regs;  in vdpu34x_h264d_wait()
1152         reg_ctx->reg_buf[task->dec.reg_index].valid = 0;  in vdpu34x_h264d_wait()