Lines Matching refs:reg_ctx
100 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu382_init() local
102 mpp_slots_set_prop(reg_ctx->slots, SLOTS_HOR_ALIGN, hevc_hor_align); in hal_h265d_vdpu382_init()
103 mpp_slots_set_prop(reg_ctx->slots, SLOTS_VER_ALIGN, hevc_ver_align); in hal_h265d_vdpu382_init()
105 reg_ctx->scaling_qm = mpp_calloc(DXVA_Qmatrix_HEVC, 1); in hal_h265d_vdpu382_init()
106 if (reg_ctx->scaling_qm == NULL) { in hal_h265d_vdpu382_init()
111 reg_ctx->scaling_rk = mpp_calloc(scalingFactor_t, 1); in hal_h265d_vdpu382_init()
112 reg_ctx->pps_buf = mpp_calloc(RK_U64, 15); in hal_h265d_vdpu382_init()
113 reg_ctx->sw_rps_buf = mpp_calloc(RK_U64, 400); in hal_h265d_vdpu382_init()
115 if (reg_ctx->scaling_rk == NULL) { in hal_h265d_vdpu382_init()
120 if (reg_ctx->group == NULL) { in hal_h265d_vdpu382_init()
121 ret = mpp_buffer_group_get_internal(®_ctx->group, MPP_BUFFER_TYPE_ION); in hal_h265d_vdpu382_init()
130 RK_U32 max_cnt = reg_ctx->fast_mode ? MAX_GEN_REG : 1; in hal_h265d_vdpu382_init()
133 ret = mpp_buffer_get(reg_ctx->group, ®_ctx->bufs, ALL_BUFFER_SIZE(max_cnt)); in hal_h265d_vdpu382_init()
139 reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs); in hal_h265d_vdpu382_init()
140 reg_ctx->offset_cabac = CABAC_TAB_OFFSET; in hal_h265d_vdpu382_init()
142 reg_ctx->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(Vdpu382H265dRegSet)); in hal_h265d_vdpu382_init()
143 reg_ctx->offset_spspps[i] = SPSPPS_OFFSET(i); in hal_h265d_vdpu382_init()
144 reg_ctx->offset_rps[i] = RPS_OFFSET(i); in hal_h265d_vdpu382_init()
145 reg_ctx->offset_sclst[i] = SCALIST_OFFSET(i); in hal_h265d_vdpu382_init()
149 if (!reg_ctx->fast_mode) { in hal_h265d_vdpu382_init()
150 reg_ctx->hw_regs = reg_ctx->g_buf[0].hw_regs; in hal_h265d_vdpu382_init()
151 reg_ctx->spspps_offset = reg_ctx->offset_spspps[0]; in hal_h265d_vdpu382_init()
152 reg_ctx->rps_offset = reg_ctx->offset_rps[0]; in hal_h265d_vdpu382_init()
153 reg_ctx->sclst_offset = reg_ctx->offset_sclst[0]; in hal_h265d_vdpu382_init()
156 ret = mpp_buffer_write(reg_ctx->bufs, 0, (void*)cabac_table, sizeof(cabac_table)); in hal_h265d_vdpu382_init()
176 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu382_deinit() local
177 RK_U32 loop = reg_ctx->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->g_buf) : 1; in hal_h265d_vdpu382_deinit()
180 if (reg_ctx->bufs) { in hal_h265d_vdpu382_deinit()
181 mpp_buffer_put(reg_ctx->bufs); in hal_h265d_vdpu382_deinit()
182 reg_ctx->bufs = NULL; in hal_h265d_vdpu382_deinit()
185 loop = reg_ctx->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->rcb_buf) : 1; in hal_h265d_vdpu382_deinit()
187 if (reg_ctx->rcb_buf[i]) { in hal_h265d_vdpu382_deinit()
188 mpp_buffer_put(reg_ctx->rcb_buf[i]); in hal_h265d_vdpu382_deinit()
189 reg_ctx->rcb_buf[i] = NULL; in hal_h265d_vdpu382_deinit()
193 if (reg_ctx->group) { in hal_h265d_vdpu382_deinit()
194 mpp_buffer_group_put(reg_ctx->group); in hal_h265d_vdpu382_deinit()
195 reg_ctx->group = NULL; in hal_h265d_vdpu382_deinit()
199 MPP_FREE(reg_ctx->g_buf[i].hw_regs); in hal_h265d_vdpu382_deinit()
201 MPP_FREE(reg_ctx->scaling_qm); in hal_h265d_vdpu382_deinit()
202 MPP_FREE(reg_ctx->scaling_rk); in hal_h265d_vdpu382_deinit()
203 MPP_FREE(reg_ctx->pps_buf); in hal_h265d_vdpu382_deinit()
204 MPP_FREE(reg_ctx->sw_rps_buf); in hal_h265d_vdpu382_deinit()
206 if (reg_ctx->cmv_bufs) { in hal_h265d_vdpu382_deinit()
207 hal_bufs_deinit(reg_ctx->cmv_bufs); in hal_h265d_vdpu382_deinit()
208 reg_ctx->cmv_bufs = NULL; in hal_h265d_vdpu382_deinit()
221 HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal; in hal_h265d_v382_output_pps_packet() local
222 Vdpu382H265dRegSet *hw_reg = (Vdpu382H265dRegSet*)(reg_ctx->hw_regs); in hal_h265d_v382_output_pps_packet()
226 if (NULL == reg_ctx || dxva_cxt == NULL) { in hal_h265d_v382_output_pps_packet()
231 void *pps_ptr = mpp_buffer_get_ptr(reg_ctx->bufs) + reg_ctx->spspps_offset; in hal_h265d_v382_output_pps_packet()
233 RK_U64 *pps_packet = reg_ctx->pps_buf; in hal_h265d_v382_output_pps_packet()
407 RK_U8 *ptr_scaling = (RK_U8 *)mpp_buffer_get_ptr(reg_ctx->bufs) + reg_ctx->sclst_offset; in hal_h265d_v382_output_pps_packet()
419 hw_reg->h265d_addr.reg180_scanlist_addr = reg_ctx->bufs_fd; in hal_h265d_v382_output_pps_packet()
423 mpp_dev_set_reg_offset(reg_ctx->dev, 180, addr + reg_ctx->sclst_offset); in hal_h265d_v382_output_pps_packet()
427 memcpy(pps_ptr + i * 112, reg_ctx->pps_buf, 112); in hal_h265d_v382_output_pps_packet()
545 HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal; in hal_h265d_rcb_info_update() local
553 if (reg_ctx->num_row_tiles != num_tiles || in hal_h265d_rcb_info_update()
554 reg_ctx->bit_depth != bit_depth || in hal_h265d_rcb_info_update()
555 reg_ctx->chroma_fmt_idc != chroma_fmt_idc || in hal_h265d_rcb_info_update()
556 reg_ctx->ctu_size != ctu_size || in hal_h265d_rcb_info_update()
557 reg_ctx->width != width || in hal_h265d_rcb_info_update()
558 reg_ctx->height != height) { in hal_h265d_rcb_info_update()
560 RK_U32 loop = reg_ctx->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->g_buf) : 1; in hal_h265d_rcb_info_update()
562 …reg_ctx->rcb_buf_size = vdpu382_get_rcb_buf_size((Vdpu382RcbInfo*)reg_ctx->rcb_info, width, height… in hal_h265d_rcb_info_update()
563 h265d_refine_rcb_size((Vdpu382RcbInfo*)reg_ctx->rcb_info, hw_regs, width, height, dxva_cxt); in hal_h265d_rcb_info_update()
568 if (reg_ctx->rcb_buf[i]) { in hal_h265d_rcb_info_update()
569 mpp_buffer_put(reg_ctx->rcb_buf[i]); in hal_h265d_rcb_info_update()
570 reg_ctx->rcb_buf[i] = NULL; in hal_h265d_rcb_info_update()
572 mpp_buffer_get(reg_ctx->group, &rcb_buf, reg_ctx->rcb_buf_size); in hal_h265d_rcb_info_update()
573 reg_ctx->rcb_buf[i] = rcb_buf; in hal_h265d_rcb_info_update()
576 reg_ctx->num_row_tiles = num_tiles; in hal_h265d_rcb_info_update()
577 reg_ctx->bit_depth = bit_depth; in hal_h265d_rcb_info_update()
578 reg_ctx->chroma_fmt_idc = chroma_fmt_idc; in hal_h265d_rcb_info_update()
579 reg_ctx->ctu_size = ctu_size; in hal_h265d_rcb_info_update()
580 reg_ctx->width = width; in hal_h265d_rcb_info_update()
581 reg_ctx->height = height; in hal_h265d_rcb_info_update()
611 HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal; in hal_h265d_vdpu382_setup_colmv_buf() local
621 RK_U32 compress = reg_ctx->hw_info ? reg_ctx->hw_info->cap_colmv_compress : 1; in hal_h265d_vdpu382_setup_colmv_buf()
626 if (reg_ctx->cmv_bufs == NULL || reg_ctx->mv_size < mv_size) { in hal_h265d_vdpu382_setup_colmv_buf()
629 if (reg_ctx->cmv_bufs) { in hal_h265d_vdpu382_setup_colmv_buf()
630 hal_bufs_deinit(reg_ctx->cmv_bufs); in hal_h265d_vdpu382_setup_colmv_buf()
631 reg_ctx->cmv_bufs = NULL; in hal_h265d_vdpu382_setup_colmv_buf()
634 hal_bufs_init(®_ctx->cmv_bufs); in hal_h265d_vdpu382_setup_colmv_buf()
635 if (reg_ctx->cmv_bufs == NULL) { in hal_h265d_vdpu382_setup_colmv_buf()
640 reg_ctx->mv_size = mv_size; in hal_h265d_vdpu382_setup_colmv_buf()
641 reg_ctx->mv_count = mpp_buf_slot_get_count(reg_ctx->slots); in hal_h265d_vdpu382_setup_colmv_buf()
642 hal_bufs_setup(reg_ctx->cmv_bufs, reg_ctx->mv_count, 1, &size); in hal_h265d_vdpu382_setup_colmv_buf()
665 HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal; in hal_h265d_vdpu382_gen_regs() local
670 (syn->dec.flags.ref_err && !reg_ctx->cfg->base.disable_error)) { in hal_h265d_vdpu382_gen_regs()
675 if (reg_ctx ->fast_mode) { in hal_h265d_vdpu382_gen_regs()
677 if (!reg_ctx->g_buf[i].use_flag) { in hal_h265d_vdpu382_gen_regs()
680 reg_ctx->spspps_offset = reg_ctx->offset_spspps[i]; in hal_h265d_vdpu382_gen_regs()
681 reg_ctx->rps_offset = reg_ctx->offset_rps[i]; in hal_h265d_vdpu382_gen_regs()
682 reg_ctx->sclst_offset = reg_ctx->offset_sclst[i]; in hal_h265d_vdpu382_gen_regs()
684 reg_ctx->hw_regs = reg_ctx->g_buf[i].hw_regs; in hal_h265d_vdpu382_gen_regs()
685 reg_ctx->g_buf[i].use_flag = 1; in hal_h265d_vdpu382_gen_regs()
696 rps_ptr = mpp_buffer_get_ptr(reg_ctx->bufs) + reg_ctx->rps_offset; in hal_h265d_vdpu382_gen_regs()
710 hw_regs = (Vdpu382H265dRegSet*)reg_ctx->hw_regs; in hal_h265d_vdpu382_gen_regs()
713 if (NULL == reg_ctx->hw_regs) { in hal_h265d_vdpu382_gen_regs()
730 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_cxt->pp.CurrPic.Index7Bits, in hal_h265d_vdpu382_gen_regs()
761 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_cxt->pp.CurrPic.Index7Bits, in hal_h265d_vdpu382_gen_regs()
772 mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, dxva_cxt->pp.CurrPic.Index7Bits); in hal_h265d_vdpu382_gen_regs()
777 mpp_buf_slot_get_prop(reg_ctx->packet_slots, syn->dec.input, SLOT_BUFFER, in hal_h265d_vdpu382_gen_regs()
784 hal_h265d_slice_hw_rps(syn->dec.syntax.data, rps_ptr, reg_ctx->sw_rps_buf, reg_ctx->fast_mode); in hal_h265d_vdpu382_gen_regs()
791 hw_regs->h265d_addr.reg197_cabactbl_base = reg_ctx->bufs_fd; in hal_h265d_vdpu382_gen_regs()
793 hw_regs->h265d_addr.reg161_pps_base = reg_ctx->bufs_fd; in hal_h265d_vdpu382_gen_regs()
794 hw_regs->h265d_addr.reg163_rps_base = reg_ctx->bufs_fd; in hal_h265d_vdpu382_gen_regs()
810 hw_regs->common.reg012.colmv_compress_en = reg_ctx->hw_info ? in hal_h265d_vdpu382_gen_regs()
811 reg_ctx->hw_info->cap_colmv_compress : 0; in hal_h265d_vdpu382_gen_regs()
835 reg_ctx->error_index[syn->dec.reg_index] = dxva_cxt->pp.CurrPic.Index7Bits; in hal_h265d_vdpu382_gen_regs()
846 mpp_buf_slot_get_prop(reg_ctx->slots, in hal_h265d_vdpu382_gen_regs()
849 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_cxt->pp.RefPicList[i].Index7Bits, in hal_h265d_vdpu382_gen_regs()
859 … reg_ctx->error_index[syn->dec.reg_index] = dxva_cxt->pp.RefPicList[i].Index7Bits; in hal_h265d_vdpu382_gen_regs()
867 mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, dxva_cxt->pp.RefPicList[i].Index7Bits); in hal_h265d_vdpu382_gen_regs()
874 if ((reg_ctx->error_index[syn->dec.reg_index] == dxva_cxt->pp.CurrPic.Index7Bits) && in hal_h265d_vdpu382_gen_regs()
887 mpp_buf_slot_get_prop(reg_ctx->slots, in hal_h265d_vdpu382_gen_regs()
891 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_cxt->pp.RefPicList[i].Index7Bits, in hal_h265d_vdpu382_gen_regs()
895 … mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index[syn->dec.reg_index]); in hal_h265d_vdpu382_gen_regs()
900 mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index[syn->dec.reg_index]); in hal_h265d_vdpu382_gen_regs()
904 if (reg_ctx->error_index[syn->dec.reg_index] == dxva_cxt->pp.CurrPic.Index7Bits) in hal_h265d_vdpu382_gen_regs()
910 mpp_dev_set_reg_offset(reg_ctx->dev, 161, reg_ctx->spspps_offset); in hal_h265d_vdpu382_gen_regs()
912 mpp_dev_set_reg_offset(reg_ctx->dev, 163, reg_ctx->rps_offset); in hal_h265d_vdpu382_gen_regs()
919 vdpu382_setup_rcb(&hw_regs->common_addr, reg_ctx->dev, reg_ctx->fast_mode ? in hal_h265d_vdpu382_gen_regs()
920 reg_ctx->rcb_buf[syn->dec.reg_index] : reg_ctx->rcb_buf[0], in hal_h265d_vdpu382_gen_regs()
921 (Vdpu382RcbInfo*)reg_ctx->rcb_info); in hal_h265d_vdpu382_gen_regs()
925 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_cxt->pp.CurrPic.Index7Bits, in hal_h265d_vdpu382_gen_regs()
933 vdpu382_setup_down_scale(mframe, reg_ctx->dev, &hw_regs->common); in hal_h265d_vdpu382_gen_regs()
941 mpp_buffer_sync_end(reg_ctx->bufs); in hal_h265d_vdpu382_gen_regs()
951 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu382_start() local
957 (task->dec.flags.ref_err && !reg_ctx->cfg->base.disable_error)) { in hal_h265d_vdpu382_start()
962 if (reg_ctx->fast_mode) { in hal_h265d_vdpu382_start()
963 p = (RK_U8*)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu382_start()
964 hw_regs = ( Vdpu382H265dRegSet *)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu382_start()
966 p = (RK_U8*)reg_ctx->hw_regs; in hal_h265d_vdpu382_start()
967 hw_regs = ( Vdpu382H265dRegSet *)reg_ctx->hw_regs; in hal_h265d_vdpu382_start()
989 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu382_start()
999 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu382_start()
1009 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu382_start()
1019 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu382_start()
1029 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu382_start()
1039 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu382_start()
1049 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_h265d_vdpu382_start()
1055 vdpu382_set_rcbinfo(reg_ctx->dev, (Vdpu382RcbInfo*)reg_ctx->rcb_info); in hal_h265d_vdpu382_start()
1057 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_CMD_SEND, NULL); in hal_h265d_vdpu382_start()
1072 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu382_wait() local
1077 if (reg_ctx->fast_mode) { in hal_h265d_vdpu382_wait()
1078 hw_regs = ( Vdpu382H265dRegSet *)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu382_wait()
1080 hw_regs = ( Vdpu382H265dRegSet *)reg_ctx->hw_regs; in hal_h265d_vdpu382_wait()
1086 (task->dec.flags.ref_err && !reg_ctx->cfg->base.disable_error)) { in hal_h265d_vdpu382_wait()
1091 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_CMD_POLL, NULL); in hal_h265d_vdpu382_wait()
1102 if (!reg_ctx->fast_mode) { in hal_h265d_vdpu382_wait()
1103 if (reg_ctx->dec_cb) in hal_h265d_vdpu382_wait()
1104 mpp_callback(reg_ctx->dec_cb, &task->dec); in hal_h265d_vdpu382_wait()
1107 mpp_buf_slot_get_prop(reg_ctx->slots, task->dec.output, in hal_h265d_vdpu382_wait()
1110 reg_ctx->fast_mode_err_found = 1; in hal_h265d_vdpu382_wait()
1115 if (reg_ctx->fast_mode && reg_ctx->fast_mode_err_found) { in hal_h265d_vdpu382_wait()
1120 mpp_buf_slot_get_prop(reg_ctx->slots, task->dec.refer[i], in hal_h265d_vdpu382_wait()
1126 mpp_buf_slot_get_prop(reg_ctx->slots, task->dec.output, in hal_h265d_vdpu382_wait()
1149 if (reg_ctx->fast_mode) { in hal_h265d_vdpu382_wait()
1150 reg_ctx->g_buf[index].use_flag = 0; in hal_h265d_vdpu382_wait()