119     Vdpu384aH264dRegCtx *ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;  in vdpu384a_setup_scale_origin_bufs()
356     Vdpu384aH264dRegCtx *ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;  in set_registers()
595     MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Vdpu384aH264dRegCtx)));  in vdpu384a_h264d_init()
596     Vdpu384aH264dRegCtx *reg_ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;  in vdpu384a_h264d_init()  local
601     FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, &reg_ctx->bufs,  in vdpu384a_h264d_init()
603     reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs);  in vdpu384a_h264d_init()
604     reg_ctx->bufs_ptr = mpp_buffer_get_ptr(reg_ctx->bufs);  in vdpu384a_h264d_init()
605     reg_ctx->offset_errinfo = VDPU384A_ERROR_INFO_OFFSET;  in vdpu384a_h264d_init()
607         reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu384aH264dRegSet, 1);  in vdpu384a_h264d_init()
608         init_ctrl_regs(reg_ctx->reg_buf[i].regs);  in vdpu384a_h264d_init()
609         reg_ctx->offset_spspps[i] = VDPU384A_SPSPPS_OFFSET(i);  in vdpu384a_h264d_init()
610         reg_ctx->offset_sclst[i] = VDPU384A_SCALING_LIST_OFFSET(i);  in vdpu384a_h264d_init()
613     mpp_buffer_attach_dev(reg_ctx->bufs, p_hal->dev);  in vdpu384a_h264d_init()
616         reg_ctx->regs = reg_ctx->reg_buf[0].regs;  in vdpu384a_h264d_init()
617         reg_ctx->spspps_offset = reg_ctx->offset_spspps[0];  in vdpu384a_h264d_init()
618         reg_ctx->sclst_offset = reg_ctx->offset_sclst[0];  in vdpu384a_h264d_init()
641     Vdpu384aH264dRegCtx *reg_ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;  in vdpu384a_h264d_deinit()  local
644     RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;  in vdpu384a_h264d_deinit()
646     if (reg_ctx->bufs) {  in vdpu384a_h264d_deinit()
647         mpp_buffer_put(reg_ctx->bufs);  in vdpu384a_h264d_deinit()
648         reg_ctx->bufs = NULL;  in vdpu384a_h264d_deinit()
652         MPP_FREE(reg_ctx->reg_buf[i].regs);  in vdpu384a_h264d_deinit()
654     loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->rcb_buf) : 1;  in vdpu384a_h264d_deinit()
656         if (reg_ctx->rcb_buf[i]) {  in vdpu384a_h264d_deinit()
657             mpp_buffer_put(reg_ctx->rcb_buf[i]);  in vdpu384a_h264d_deinit()
658             reg_ctx->rcb_buf[i] = NULL;  in vdpu384a_h264d_deinit()
667     if (reg_ctx->origin_bufs) {  in vdpu384a_h264d_deinit()
668         hal_bufs_deinit(reg_ctx->origin_bufs);  in vdpu384a_h264d_deinit()
669         reg_ctx->origin_bufs = NULL;  in vdpu384a_h264d_deinit()
672     MPP_FREE(p_hal->reg_ctx);  in vdpu384a_h264d_deinit()
731     Vdpu384aH264dRegCtx *ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;  in hal_h264d_rcb_info_update()
770     Vdpu384aH264dRegCtx *ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;  in vdpu384a_h264d_gen_regs()
878     Vdpu384aH264dRegCtx *reg_ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;  in vdpu384a_h264d_start()  local
880                                 reg_ctx->reg_buf[task->dec.reg_index].regs :  in vdpu384a_h264d_start()
881                                 reg_ctx->regs;  in vdpu384a_h264d_start()
934         vdpu384a_set_rcbinfo(dev, (Vdpu384aRcbInfo*)reg_ctx->rcb_info);  in vdpu384a_h264d_start()
954     Vdpu384aH264dRegCtx *reg_ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;  in vdpu384a_h264d_wait()  local
956                                   reg_ctx->reg_buf[task->dec.reg_index].regs :  in vdpu384a_h264d_wait()
957                                   reg_ctx->regs;  in vdpu384a_h264d_wait()
990         reg_ctx->reg_buf[task->dec.reg_index].valid = 0;  in vdpu384a_h264d_wait()