Lines Matching refs:reg_ctx
102 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu34x_init() local
104 mpp_slots_set_prop(reg_ctx->slots, SLOTS_HOR_ALIGN, hevc_hor_align); in hal_h265d_vdpu34x_init()
105 mpp_slots_set_prop(reg_ctx->slots, SLOTS_VER_ALIGN, hevc_ver_align); in hal_h265d_vdpu34x_init()
107 reg_ctx->scaling_qm = mpp_calloc(DXVA_Qmatrix_HEVC, 1); in hal_h265d_vdpu34x_init()
108 if (reg_ctx->scaling_qm == NULL) { in hal_h265d_vdpu34x_init()
113 reg_ctx->scaling_rk = mpp_calloc(scalingFactor_t, 1); in hal_h265d_vdpu34x_init()
114 reg_ctx->pps_buf = mpp_calloc(RK_U64, 15); in hal_h265d_vdpu34x_init()
115 reg_ctx->sw_rps_buf = mpp_calloc(RK_U64, 400); in hal_h265d_vdpu34x_init()
117 if (reg_ctx->scaling_rk == NULL) { in hal_h265d_vdpu34x_init()
122 if (reg_ctx->group == NULL) { in hal_h265d_vdpu34x_init()
123 ret = mpp_buffer_group_get_internal(®_ctx->group, MPP_BUFFER_TYPE_ION); in hal_h265d_vdpu34x_init()
132 RK_U32 max_cnt = reg_ctx->fast_mode ? MAX_GEN_REG : 1; in hal_h265d_vdpu34x_init()
135 ret = mpp_buffer_get(reg_ctx->group, ®_ctx->bufs, ALL_BUFFER_SIZE(max_cnt)); in hal_h265d_vdpu34x_init()
141 reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs); in hal_h265d_vdpu34x_init()
142 reg_ctx->offset_cabac = CABAC_TAB_OFFSET; in hal_h265d_vdpu34x_init()
144 reg_ctx->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(Vdpu34xH265dRegSet)); in hal_h265d_vdpu34x_init()
145 reg_ctx->offset_spspps[i] = SPSPPS_OFFSET(i); in hal_h265d_vdpu34x_init()
146 reg_ctx->offset_rps[i] = RPS_OFFSET(i); in hal_h265d_vdpu34x_init()
147 reg_ctx->offset_sclst[i] = SCALIST_OFFSET(i); in hal_h265d_vdpu34x_init()
151 if (!reg_ctx->fast_mode) { in hal_h265d_vdpu34x_init()
152 reg_ctx->hw_regs = reg_ctx->g_buf[0].hw_regs; in hal_h265d_vdpu34x_init()
153 reg_ctx->spspps_offset = reg_ctx->offset_spspps[0]; in hal_h265d_vdpu34x_init()
154 reg_ctx->rps_offset = reg_ctx->offset_rps[0]; in hal_h265d_vdpu34x_init()
155 reg_ctx->sclst_offset = reg_ctx->offset_sclst[0]; in hal_h265d_vdpu34x_init()
158 ret = mpp_buffer_write(reg_ctx->bufs, 0, (void*)cabac_table, sizeof(cabac_table)); in hal_h265d_vdpu34x_init()
178 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu34x_deinit() local
179 RK_U32 loop = reg_ctx->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->g_buf) : 1; in hal_h265d_vdpu34x_deinit()
182 if (reg_ctx->bufs) { in hal_h265d_vdpu34x_deinit()
183 mpp_buffer_put(reg_ctx->bufs); in hal_h265d_vdpu34x_deinit()
184 reg_ctx->bufs = NULL; in hal_h265d_vdpu34x_deinit()
187 loop = reg_ctx->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->rcb_buf) : 1; in hal_h265d_vdpu34x_deinit()
189 if (reg_ctx->rcb_buf[i]) { in hal_h265d_vdpu34x_deinit()
190 mpp_buffer_put(reg_ctx->rcb_buf[i]); in hal_h265d_vdpu34x_deinit()
191 reg_ctx->rcb_buf[i] = NULL; in hal_h265d_vdpu34x_deinit()
195 if (reg_ctx->missing_ref_buf) { in hal_h265d_vdpu34x_deinit()
196 mpp_buffer_put(reg_ctx->missing_ref_buf); in hal_h265d_vdpu34x_deinit()
197 reg_ctx->missing_ref_buf = NULL; in hal_h265d_vdpu34x_deinit()
200 if (reg_ctx->group) { in hal_h265d_vdpu34x_deinit()
201 mpp_buffer_group_put(reg_ctx->group); in hal_h265d_vdpu34x_deinit()
202 reg_ctx->group = NULL; in hal_h265d_vdpu34x_deinit()
206 MPP_FREE(reg_ctx->g_buf[i].hw_regs); in hal_h265d_vdpu34x_deinit()
208 MPP_FREE(reg_ctx->scaling_qm); in hal_h265d_vdpu34x_deinit()
209 MPP_FREE(reg_ctx->scaling_rk); in hal_h265d_vdpu34x_deinit()
210 MPP_FREE(reg_ctx->pps_buf); in hal_h265d_vdpu34x_deinit()
211 MPP_FREE(reg_ctx->sw_rps_buf); in hal_h265d_vdpu34x_deinit()
213 if (reg_ctx->cmv_bufs) { in hal_h265d_vdpu34x_deinit()
214 hal_bufs_deinit(reg_ctx->cmv_bufs); in hal_h265d_vdpu34x_deinit()
215 reg_ctx->cmv_bufs = NULL; in hal_h265d_vdpu34x_deinit()
228 HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal; in hal_h265d_v345_output_pps_packet() local
229 Vdpu34xH265dRegSet *hw_reg = (Vdpu34xH265dRegSet*)(reg_ctx->hw_regs); in hal_h265d_v345_output_pps_packet()
233 if (NULL == reg_ctx || dxva_cxt == NULL) { in hal_h265d_v345_output_pps_packet()
238 void *pps_ptr = mpp_buffer_get_ptr(reg_ctx->bufs) + reg_ctx->spspps_offset; in hal_h265d_v345_output_pps_packet()
240 RK_U64 *pps_packet = reg_ctx->pps_buf; in hal_h265d_v345_output_pps_packet()
414 RK_U8 *ptr_scaling = (RK_U8 *)mpp_buffer_get_ptr(reg_ctx->bufs) + reg_ctx->sclst_offset; in hal_h265d_v345_output_pps_packet()
426 hw_reg->h265d_addr.reg180_scanlist_addr = reg_ctx->bufs_fd; in hal_h265d_v345_output_pps_packet()
430 mpp_dev_set_reg_offset(reg_ctx->dev, 180, addr + reg_ctx->sclst_offset); in hal_h265d_v345_output_pps_packet()
434 memcpy(pps_ptr + i * 112, reg_ctx->pps_buf, 112); in hal_h265d_v345_output_pps_packet()
452 HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal; in hal_h265d_output_pps_packet() local
456 if (NULL == reg_ctx || dxva_cxt == NULL) { in hal_h265d_output_pps_packet()
462 void *pps_ptr = mpp_buffer_get_ptr(reg_ctx->bufs) + reg_ctx->spspps_offset; in hal_h265d_output_pps_packet()
465 RK_U64 *pps_packet = reg_ctx->pps_buf; in hal_h265d_output_pps_packet()
635 RK_U8 *ptr_scaling = (RK_U8 *)mpp_buffer_get_ptr(reg_ctx->scaling_list_data); in hal_h265d_output_pps_packet()
646 RK_U32 fd = mpp_buffer_get_fd(reg_ctx->scaling_list_data); in hal_h265d_output_pps_packet()
654 memcpy(pps_ptr + i * 80, reg_ctx->pps_buf, 80); in hal_h265d_output_pps_packet()
655 } else if (reg_ctx->fast_mode) { in hal_h265d_output_pps_packet()
657 memcpy(pps_ptr + i * 80, reg_ctx->pps_buf, 80); in hal_h265d_output_pps_packet()
774 HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal; in hal_h265d_rcb_info_update() local
782 if (reg_ctx->num_row_tiles != num_tiles || in hal_h265d_rcb_info_update()
783 reg_ctx->bit_depth != bit_depth || in hal_h265d_rcb_info_update()
784 reg_ctx->chroma_fmt_idc != chroma_fmt_idc || in hal_h265d_rcb_info_update()
785 reg_ctx->ctu_size != ctu_size || in hal_h265d_rcb_info_update()
786 reg_ctx->width != width || in hal_h265d_rcb_info_update()
787 reg_ctx->height != height) { in hal_h265d_rcb_info_update()
789 RK_U32 loop = reg_ctx->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->g_buf) : 1; in hal_h265d_rcb_info_update()
791 …reg_ctx->rcb_buf_size = vdpu34x_get_rcb_buf_size((Vdpu34xRcbInfo*)reg_ctx->rcb_info, width, height… in hal_h265d_rcb_info_update()
792 h265d_refine_rcb_size((Vdpu34xRcbInfo*)reg_ctx->rcb_info, hw_regs, width, height, dxva_cxt); in hal_h265d_rcb_info_update()
797 if (reg_ctx->rcb_buf[i]) { in hal_h265d_rcb_info_update()
798 mpp_buffer_put(reg_ctx->rcb_buf[i]); in hal_h265d_rcb_info_update()
799 reg_ctx->rcb_buf[i] = NULL; in hal_h265d_rcb_info_update()
801 mpp_buffer_get(reg_ctx->group, &rcb_buf, reg_ctx->rcb_buf_size); in hal_h265d_rcb_info_update()
802 reg_ctx->rcb_buf[i] = rcb_buf; in hal_h265d_rcb_info_update()
805 reg_ctx->num_row_tiles = num_tiles; in hal_h265d_rcb_info_update()
806 reg_ctx->bit_depth = bit_depth; in hal_h265d_rcb_info_update()
807 reg_ctx->chroma_fmt_idc = chroma_fmt_idc; in hal_h265d_rcb_info_update()
808 reg_ctx->ctu_size = ctu_size; in hal_h265d_rcb_info_update()
809 reg_ctx->width = width; in hal_h265d_rcb_info_update()
810 reg_ctx->height = height; in hal_h265d_rcb_info_update()
856 HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal; in hal_h265d_vdpu34x_gen_regs() local
864 (syn->dec.flags.ref_err && !reg_ctx->cfg->base.disable_error)) { in hal_h265d_vdpu34x_gen_regs()
869 if (reg_ctx ->fast_mode) { in hal_h265d_vdpu34x_gen_regs()
871 if (!reg_ctx->g_buf[i].use_flag) { in hal_h265d_vdpu34x_gen_regs()
874 reg_ctx->spspps_offset = reg_ctx->offset_spspps[i]; in hal_h265d_vdpu34x_gen_regs()
875 reg_ctx->rps_offset = reg_ctx->offset_rps[i]; in hal_h265d_vdpu34x_gen_regs()
876 reg_ctx->sclst_offset = reg_ctx->offset_sclst[i]; in hal_h265d_vdpu34x_gen_regs()
878 reg_ctx->hw_regs = reg_ctx->g_buf[i].hw_regs; in hal_h265d_vdpu34x_gen_regs()
879 reg_ctx->g_buf[i].use_flag = 1; in hal_h265d_vdpu34x_gen_regs()
890 rps_ptr = mpp_buffer_get_ptr(reg_ctx->bufs) + reg_ctx->rps_offset; in hal_h265d_vdpu34x_gen_regs()
904 hw_regs = (Vdpu34xH265dRegSet*)reg_ctx->hw_regs; in hal_h265d_vdpu34x_gen_regs()
907 if (NULL == reg_ctx->hw_regs) { in hal_h265d_vdpu34x_gen_regs()
916 if (reg_ctx->cmv_bufs == NULL || reg_ctx->mv_size < mv_size) { in hal_h265d_vdpu34x_gen_regs()
919 if (reg_ctx->cmv_bufs) { in hal_h265d_vdpu34x_gen_regs()
920 hal_bufs_deinit(reg_ctx->cmv_bufs); in hal_h265d_vdpu34x_gen_regs()
921 reg_ctx->cmv_bufs = NULL; in hal_h265d_vdpu34x_gen_regs()
924 hal_bufs_init(®_ctx->cmv_bufs); in hal_h265d_vdpu34x_gen_regs()
925 if (reg_ctx->cmv_bufs == NULL) { in hal_h265d_vdpu34x_gen_regs()
930 reg_ctx->mv_size = mv_size; in hal_h265d_vdpu34x_gen_regs()
931 reg_ctx->mv_count = mpp_buf_slot_get_count(reg_ctx->slots); in hal_h265d_vdpu34x_gen_regs()
932 hal_bufs_setup(reg_ctx->cmv_bufs, reg_ctx->mv_count, 1, &size); in hal_h265d_vdpu34x_gen_regs()
939 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_cxt->pp.CurrPic.Index7Bits, in hal_h265d_vdpu34x_gen_regs()
972 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_cxt->pp.CurrPic.Index7Bits, in hal_h265d_vdpu34x_gen_regs()
983 mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, dxva_cxt->pp.CurrPic.Index7Bits); in hal_h265d_vdpu34x_gen_regs()
988 mpp_buf_slot_get_prop(reg_ctx->packet_slots, syn->dec.input, SLOT_BUFFER, in hal_h265d_vdpu34x_gen_regs()
993 if (reg_ctx->is_v34x) { in hal_h265d_vdpu34x_gen_regs()
997 … hal_h265d_slice_hw_rps(syn->dec.syntax.data, rps_ptr, reg_ctx->sw_rps_buf, reg_ctx->fast_mode); in hal_h265d_vdpu34x_gen_regs()
1007 hw_regs->h265d_addr.reg197_cabactbl_base = reg_ctx->bufs_fd; in hal_h265d_vdpu34x_gen_regs()
1009 hw_regs->h265d_addr.reg161_pps_base = reg_ctx->bufs_fd; in hal_h265d_vdpu34x_gen_regs()
1010 hw_regs->h265d_addr.reg163_rps_base = reg_ctx->bufs_fd; in hal_h265d_vdpu34x_gen_regs()
1047 reg_ctx->error_index[syn->dec.reg_index] = dxva_cxt->pp.CurrPic.Index7Bits; in hal_h265d_vdpu34x_gen_regs()
1057 mpp_buf_slot_get_prop(reg_ctx->slots, in hal_h265d_vdpu34x_gen_regs()
1060 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_cxt->pp.RefPicList[i].Index7Bits, in hal_h265d_vdpu34x_gen_regs()
1063 reg_ctx->cfg->base.disable_error) { in hal_h265d_vdpu34x_gen_regs()
1064 … if (reg_ctx->missing_ref_buf && reg_ctx->missing_ref_buf_size < mpp_buffer_get_size(framebuf)) { in hal_h265d_vdpu34x_gen_regs()
1065 mpp_buffer_put(reg_ctx->missing_ref_buf); in hal_h265d_vdpu34x_gen_regs()
1066 reg_ctx->missing_ref_buf = NULL; in hal_h265d_vdpu34x_gen_regs()
1069 if (!reg_ctx->missing_ref_buf) { in hal_h265d_vdpu34x_gen_regs()
1070 reg_ctx->missing_ref_buf_size = mpp_buffer_get_size(framebuf); in hal_h265d_vdpu34x_gen_regs()
1071 … mpp_buffer_get(reg_ctx->group, ®_ctx->missing_ref_buf, reg_ctx->missing_ref_buf_size); in hal_h265d_vdpu34x_gen_regs()
1072 if (!reg_ctx->missing_ref_buf) { in hal_h265d_vdpu34x_gen_regs()
1078 ref_buf = reg_ctx->missing_ref_buf; in hal_h265d_vdpu34x_gen_regs()
1088 … reg_ctx->error_index[syn->dec.reg_index] = dxva_cxt->pp.RefPicList[i].Index7Bits; in hal_h265d_vdpu34x_gen_regs()
1100 mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, dxva_cxt->pp.RefPicList[i].Index7Bits); in hal_h265d_vdpu34x_gen_regs()
1108 … mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index[syn->dec.reg_index]); in hal_h265d_vdpu34x_gen_regs()
1112 mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index[syn->dec.reg_index]); in hal_h265d_vdpu34x_gen_regs()
1115 if (reg_ctx->error_index[syn->dec.reg_index] == dxva_cxt->pp.CurrPic.Index7Bits) in hal_h265d_vdpu34x_gen_regs()
1121 if ((reg_ctx->error_index[syn->dec.reg_index] == dxva_cxt->pp.CurrPic.Index7Bits) && in hal_h265d_vdpu34x_gen_regs()
1128 if (reg_ctx->is_v34x) { in hal_h265d_vdpu34x_gen_regs()
1134 mpp_dev_set_reg_offset(reg_ctx->dev, 161, reg_ctx->spspps_offset); in hal_h265d_vdpu34x_gen_regs()
1136 mpp_dev_set_reg_offset(reg_ctx->dev, 163, reg_ctx->rps_offset); in hal_h265d_vdpu34x_gen_regs()
1144 vdpu34x_setup_rcb(&hw_regs->common_addr, reg_ctx->dev, reg_ctx->fast_mode ? in hal_h265d_vdpu34x_gen_regs()
1145 reg_ctx->rcb_buf[syn->dec.reg_index] : reg_ctx->rcb_buf[0], in hal_h265d_vdpu34x_gen_regs()
1146 (Vdpu34xRcbInfo*)reg_ctx->rcb_info); in hal_h265d_vdpu34x_gen_regs()
1148 mpp_buffer_sync_end(reg_ctx->bufs); in hal_h265d_vdpu34x_gen_regs()
1158 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu34x_start() local
1164 (task->dec.flags.ref_err && !reg_ctx->cfg->base.disable_error)) { in hal_h265d_vdpu34x_start()
1169 if (reg_ctx->fast_mode) { in hal_h265d_vdpu34x_start()
1170 p = (RK_U8*)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu34x_start()
1171 hw_regs = ( Vdpu34xH265dRegSet *)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu34x_start()
1173 p = (RK_U8*)reg_ctx->hw_regs; in hal_h265d_vdpu34x_start()
1174 hw_regs = ( Vdpu34xH265dRegSet *)reg_ctx->hw_regs; in hal_h265d_vdpu34x_start()
1196 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu34x_start()
1206 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu34x_start()
1216 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu34x_start()
1226 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu34x_start()
1236 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu34x_start()
1247 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu34x_start()
1258 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_h265d_vdpu34x_start()
1265 vdpu34x_set_rcbinfo(reg_ctx->dev, (Vdpu34xRcbInfo*)reg_ctx->rcb_info); in hal_h265d_vdpu34x_start()
1267 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_CMD_SEND, NULL); in hal_h265d_vdpu34x_start()
1282 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu34x_wait() local
1287 if (reg_ctx->fast_mode) { in hal_h265d_vdpu34x_wait()
1288 hw_regs = ( Vdpu34xH265dRegSet *)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu34x_wait()
1290 hw_regs = ( Vdpu34xH265dRegSet *)reg_ctx->hw_regs; in hal_h265d_vdpu34x_wait()
1296 (task->dec.flags.ref_err && !reg_ctx->cfg->base.disable_error)) { in hal_h265d_vdpu34x_wait()
1301 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_CMD_POLL, NULL); in hal_h265d_vdpu34x_wait()
1312 if (!reg_ctx->fast_mode) { in hal_h265d_vdpu34x_wait()
1313 if (reg_ctx->dec_cb) in hal_h265d_vdpu34x_wait()
1314 mpp_callback(reg_ctx->dec_cb, &task->dec); in hal_h265d_vdpu34x_wait()
1317 mpp_buf_slot_get_prop(reg_ctx->slots, task->dec.output, in hal_h265d_vdpu34x_wait()
1320 reg_ctx->fast_mode_err_found = 1; in hal_h265d_vdpu34x_wait()
1325 if (reg_ctx->fast_mode && reg_ctx->fast_mode_err_found) { in hal_h265d_vdpu34x_wait()
1330 mpp_buf_slot_get_prop(reg_ctx->slots, task->dec.refer[i], in hal_h265d_vdpu34x_wait()
1336 mpp_buf_slot_get_prop(reg_ctx->slots, task->dec.output, in hal_h265d_vdpu34x_wait()
1359 if (reg_ctx->fast_mode) { in hal_h265d_vdpu34x_wait()
1360 reg_ctx->g_buf[index].use_flag = 0; in hal_h265d_vdpu34x_wait()