459         H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;  in set_vlc_regs()  local
460         RK_U32 *ptr = (RK_U32 *)reg_ctx->poc_ptr;  in set_vlc_regs()
483             H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;  in set_vlc_regs()  local
484             RK_U32 *ptr_tmp = (RK_U32 *)reg_ctx->poc_ptr;  in set_vlc_regs()
760         H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;  in set_asic_regs()  local
763             RK_U32 *ptr = (RK_U32 *)reg_ctx->sclst_ptr;  in set_asic_regs()
784         p_regs->sw61.qtable_st_adr = mpp_buffer_get_fd(reg_ctx->buf);  in set_asic_regs()
809     MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(H264dVdpuRegCtx_t)));  in vdpu2_h264d_init()
810     H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;  in vdpu2_h264d_init()  local
814         RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;  in vdpu2_h264d_init()
818             FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, &reg_ctx->reg_buf[i].buf,  buf_size));  in vdpu2_h264d_init()
819             reg_ctx->reg_buf[i].cabac_ptr = mpp_buffer_get_ptr(reg_ctx->reg_buf[i].buf);  in vdpu2_h264d_init()
820             reg_ctx->reg_buf[i].poc_ptr = reg_ctx->reg_buf[i].cabac_ptr + VDPU_CABAC_TAB_SIZE;  in vdpu2_h264d_init()
821             reg_ctx->reg_buf[i].sclst_ptr = reg_ctx->reg_buf[i].poc_ptr + VDPU_POC_BUF_SIZE;  in vdpu2_h264d_init()
822             reg_ctx->reg_buf[i].regs = mpp_calloc_size(void, sizeof(H264dVdpuRegs_t));  in vdpu2_h264d_init()
824 …        memcpy(reg_ctx->reg_buf[i].cabac_ptr, (void *)vdpu_cabac_table,  sizeof(vdpu_cabac_table));  in vdpu2_h264d_init()
829         reg_ctx->buf = reg_ctx->reg_buf[0].buf;  in vdpu2_h264d_init()
830         reg_ctx->cabac_ptr = reg_ctx->reg_buf[0].cabac_ptr;  in vdpu2_h264d_init()
831         reg_ctx->poc_ptr = reg_ctx->reg_buf[0].poc_ptr;  in vdpu2_h264d_init()
832         reg_ctx->sclst_ptr = reg_ctx->reg_buf[0].sclst_ptr;  in vdpu2_h264d_init()
833         reg_ctx->regs = reg_ctx->reg_buf[0].regs;  in vdpu2_h264d_init()
858     H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;  in vdpu2_h264d_deinit()  local
861     RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;  in vdpu2_h264d_deinit()
863         MPP_FREE(reg_ctx->reg_buf[i].regs);  in vdpu2_h264d_deinit()
864         mpp_buffer_put(reg_ctx->reg_buf[i].buf);  in vdpu2_h264d_deinit()
867     MPP_FREE(p_hal->reg_ctx);  in vdpu2_h264d_deinit()
895     H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;  in vdpu2_h264d_gen_regs()  local
898         for (i = 0; i <  MPP_ARRAY_ELEMS(reg_ctx->reg_buf); i++) {  in vdpu2_h264d_gen_regs()
899             if (!reg_ctx->reg_buf[i].valid) {  in vdpu2_h264d_gen_regs()
901                 reg_ctx->buf = reg_ctx->reg_buf[i].buf;  in vdpu2_h264d_gen_regs()
902                 reg_ctx->cabac_ptr = reg_ctx->reg_buf[i].cabac_ptr;  in vdpu2_h264d_gen_regs()
903                 reg_ctx->poc_ptr = reg_ctx->reg_buf[i].poc_ptr;  in vdpu2_h264d_gen_regs()
904                 reg_ctx->sclst_ptr = reg_ctx->reg_buf[i].sclst_ptr;  in vdpu2_h264d_gen_regs()
905                 reg_ctx->regs = reg_ctx->reg_buf[i].regs;  in vdpu2_h264d_gen_regs()
906                 reg_ctx->reg_buf[i].valid = 1;  in vdpu2_h264d_gen_regs()
913     FUN_CHECK(ret = set_device_regs(p_hal, (H264dVdpuRegs_t *)reg_ctx->regs));  in vdpu2_h264d_gen_regs()
914     FUN_CHECK(ret = set_pic_regs(p_hal, (H264dVdpuRegs_t *)reg_ctx->regs));  in vdpu2_h264d_gen_regs()
915     FUN_CHECK(ret = set_vlc_regs(p_hal, (H264dVdpuRegs_t *)reg_ctx->regs));  in vdpu2_h264d_gen_regs()
916     FUN_CHECK(ret = set_ref_regs(p_hal, (H264dVdpuRegs_t *)reg_ctx->regs));  in vdpu2_h264d_gen_regs()
917     FUN_CHECK(ret = set_asic_regs(p_hal, (H264dVdpuRegs_t *)reg_ctx->regs));  in vdpu2_h264d_gen_regs()
918     mpp_buffer_sync_end(reg_ctx->buf);  in vdpu2_h264d_gen_regs()
936     H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;  in vdpu2_h264d_start()  local
938                               (H264dVdpuRegs_t *)reg_ctx->reg_buf[task->dec.reg_index].regs :  in vdpu2_h264d_start()
939                               (H264dVdpuRegs_t *)reg_ctx->regs;  in vdpu2_h264d_start()
969         RK_U32 *reg_tmp = (RK_U32*)reg_ctx->regs;  in vdpu2_h264d_start()
988         wr_cfg.reg = reg_ctx->regs;  in vdpu2_h264d_start()
998         rd_cfg.reg = reg_ctx->regs;  in vdpu2_h264d_start()
1030     H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;  in vdpu2_h264d_wait()  local
1032                                                   reg_ctx->reg_buf[task->dec.reg_index].regs :  in vdpu2_h264d_wait()
1033                                                   reg_ctx->regs);  in vdpu2_h264d_wait()
1049         param.regs = (RK_U32 *)reg_ctx->regs;  in vdpu2_h264d_wait()
1056         reg_ctx->reg_buf[task->dec.reg_index].valid = 0;  in vdpu2_h264d_wait()