Lines Matching refs:reg_ctx
91 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu384a_init() local
93 mpp_slots_set_prop(reg_ctx->slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64); in hal_h265d_vdpu384a_init()
94 mpp_slots_set_prop(reg_ctx->slots, SLOTS_VER_ALIGN, hevc_ver_align); in hal_h265d_vdpu384a_init()
96 reg_ctx->scaling_qm = mpp_calloc(DXVA_Qmatrix_HEVC, 1); in hal_h265d_vdpu384a_init()
97 if (reg_ctx->scaling_qm == NULL) { in hal_h265d_vdpu384a_init()
102 reg_ctx->scaling_rk = mpp_calloc(scalingFactor_t, 1); in hal_h265d_vdpu384a_init()
103 reg_ctx->pps_buf = mpp_calloc(RK_U8, SPSPPS_ALIGNED_SIZE); in hal_h265d_vdpu384a_init()
105 if (reg_ctx->scaling_rk == NULL) { in hal_h265d_vdpu384a_init()
110 if (reg_ctx->group == NULL) { in hal_h265d_vdpu384a_init()
111 ret = mpp_buffer_group_get_internal(®_ctx->group, MPP_BUFFER_TYPE_ION); in hal_h265d_vdpu384a_init()
120 RK_U32 max_cnt = reg_ctx->fast_mode ? MAX_GEN_REG : 1; in hal_h265d_vdpu384a_init()
123 ret = mpp_buffer_get(reg_ctx->group, ®_ctx->bufs, ALL_BUFFER_SIZE(max_cnt)); in hal_h265d_vdpu384a_init()
129 reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs); in hal_h265d_vdpu384a_init()
131 reg_ctx->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(Vdpu384aH265dRegSet)); in hal_h265d_vdpu384a_init()
132 reg_ctx->offset_spspps[i] = SPSPPS_OFFSET(i); in hal_h265d_vdpu384a_init()
133 reg_ctx->offset_sclst[i] = SCALIST_OFFSET(i); in hal_h265d_vdpu384a_init()
136 mpp_buffer_attach_dev(reg_ctx->bufs, reg_ctx->dev); in hal_h265d_vdpu384a_init()
139 if (!reg_ctx->fast_mode) { in hal_h265d_vdpu384a_init()
140 reg_ctx->hw_regs = reg_ctx->g_buf[0].hw_regs; in hal_h265d_vdpu384a_init()
141 reg_ctx->spspps_offset = reg_ctx->offset_spspps[0]; in hal_h265d_vdpu384a_init()
142 reg_ctx->sclst_offset = reg_ctx->offset_sclst[0]; in hal_h265d_vdpu384a_init()
156 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu384a_deinit() local
157 RK_U32 loop = reg_ctx->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->g_buf) : 1; in hal_h265d_vdpu384a_deinit()
160 if (reg_ctx->bufs) { in hal_h265d_vdpu384a_deinit()
161 mpp_buffer_put(reg_ctx->bufs); in hal_h265d_vdpu384a_deinit()
162 reg_ctx->bufs = NULL; in hal_h265d_vdpu384a_deinit()
165 loop = reg_ctx->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->rcb_buf) : 1; in hal_h265d_vdpu384a_deinit()
167 if (reg_ctx->rcb_buf[i]) { in hal_h265d_vdpu384a_deinit()
168 mpp_buffer_put(reg_ctx->rcb_buf[i]); in hal_h265d_vdpu384a_deinit()
169 reg_ctx->rcb_buf[i] = NULL; in hal_h265d_vdpu384a_deinit()
173 if (reg_ctx->group) { in hal_h265d_vdpu384a_deinit()
174 mpp_buffer_group_put(reg_ctx->group); in hal_h265d_vdpu384a_deinit()
175 reg_ctx->group = NULL; in hal_h265d_vdpu384a_deinit()
179 MPP_FREE(reg_ctx->g_buf[i].hw_regs); in hal_h265d_vdpu384a_deinit()
181 MPP_FREE(reg_ctx->scaling_qm); in hal_h265d_vdpu384a_deinit()
182 MPP_FREE(reg_ctx->scaling_rk); in hal_h265d_vdpu384a_deinit()
183 MPP_FREE(reg_ctx->pps_buf); in hal_h265d_vdpu384a_deinit()
185 if (reg_ctx->cmv_bufs) { in hal_h265d_vdpu384a_deinit()
186 hal_bufs_deinit(reg_ctx->cmv_bufs); in hal_h265d_vdpu384a_deinit()
187 reg_ctx->cmv_bufs = NULL; in hal_h265d_vdpu384a_deinit()
190 if (reg_ctx->origin_bufs) { in hal_h265d_vdpu384a_deinit()
191 hal_bufs_deinit(reg_ctx->origin_bufs); in hal_h265d_vdpu384a_deinit()
192 reg_ctx->origin_bufs = NULL; in hal_h265d_vdpu384a_deinit()
299 HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal; in hal_h265d_vdpu384a_scalinglist_packet() local
305 if (memcmp((void*)&dxva_ctx->qm, reg_ctx->scaling_qm, sizeof(DXVA_Qmatrix_HEVC))) { in hal_h265d_vdpu384a_scalinglist_packet()
335 hal_vdpu384a_record_scaling_list((scalingFactor_t *)reg_ctx->scaling_rk, &sl); in hal_h265d_vdpu384a_scalinglist_packet()
338 memcpy(ptr, reg_ctx->scaling_rk, sizeof(scalingFactor_t)); in hal_h265d_vdpu384a_scalinglist_packet()
348 HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal; in hal_h265d_v345_output_pps_packet() local
349 Vdpu384aH265dRegSet *hw_reg = (Vdpu384aH265dRegSet*)(reg_ctx->hw_regs); in hal_h265d_v345_output_pps_packet()
353 if (NULL == reg_ctx || dxva_ctx == NULL) { in hal_h265d_v345_output_pps_packet()
361 void *pps_ptr = mpp_buffer_get_ptr(reg_ctx->bufs) + reg_ctx->spspps_offset; in hal_h265d_v345_output_pps_packet()
362 RK_U64 *pps_packet = reg_ctx->pps_buf; in hal_h265d_v345_output_pps_packet()
605 memcpy(pps_ptr, reg_ctx->pps_buf, SPSPPS_ALIGNED_SIZE); in hal_h265d_v345_output_pps_packet()
610 RK_U8 *ptr_scaling = (RK_U8 *)mpp_buffer_get_ptr(reg_ctx->bufs) + reg_ctx->sclst_offset; in hal_h265d_v345_output_pps_packet()
622 hw_reg->common_addr.reg132_scanlist_addr = reg_ctx->bufs_fd; in hal_h265d_v345_output_pps_packet()
623 mpp_dev_set_reg_offset(reg_ctx->dev, 132, addr + reg_ctx->sclst_offset); in hal_h265d_v345_output_pps_packet()
725 HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal; in hal_h265d_rcb_info_update() local
734 if (reg_ctx->num_row_tiles != num_tiles || in hal_h265d_rcb_info_update()
735 reg_ctx->bit_depth != bit_depth || in hal_h265d_rcb_info_update()
736 reg_ctx->chroma_fmt_idc != chroma_fmt_idc || in hal_h265d_rcb_info_update()
737 reg_ctx->ctu_size != ctu_size || in hal_h265d_rcb_info_update()
738 reg_ctx->width != width || in hal_h265d_rcb_info_update()
739 reg_ctx->height != height) { in hal_h265d_rcb_info_update()
741 RK_U32 loop = reg_ctx->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->g_buf) : 1; in hal_h265d_rcb_info_update()
743 …reg_ctx->rcb_buf_size = vdpu384a_get_rcb_buf_size((Vdpu384aRcbInfo *)reg_ctx->rcb_info, width, hei… in hal_h265d_rcb_info_update()
744 h265d_refine_rcb_size((Vdpu384aRcbInfo *)reg_ctx->rcb_info, width, height, dxva_ctx); in hal_h265d_rcb_info_update()
750 if (reg_ctx->rcb_buf[i]) { in hal_h265d_rcb_info_update()
751 mpp_buffer_put(reg_ctx->rcb_buf[i]); in hal_h265d_rcb_info_update()
752 reg_ctx->rcb_buf[i] = NULL; in hal_h265d_rcb_info_update()
754 mpp_buffer_get(reg_ctx->group, &rcb_buf, reg_ctx->rcb_buf_size); in hal_h265d_rcb_info_update()
755 reg_ctx->rcb_buf[i] = rcb_buf; in hal_h265d_rcb_info_update()
758 reg_ctx->num_row_tiles = num_tiles; in hal_h265d_rcb_info_update()
759 reg_ctx->bit_depth = bit_depth; in hal_h265d_rcb_info_update()
760 reg_ctx->chroma_fmt_idc = chroma_fmt_idc; in hal_h265d_rcb_info_update()
761 reg_ctx->ctu_size = ctu_size; in hal_h265d_rcb_info_update()
762 reg_ctx->width = width; in hal_h265d_rcb_info_update()
763 reg_ctx->height = height; in hal_h265d_rcb_info_update()
793 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu384a_gen_regs() local
797 (syn->dec.flags.ref_err && !reg_ctx->cfg->base.disable_error)) { in hal_h265d_vdpu384a_gen_regs()
805 if (reg_ctx ->fast_mode) { in hal_h265d_vdpu384a_gen_regs()
807 if (!reg_ctx->g_buf[i].use_flag) { in hal_h265d_vdpu384a_gen_regs()
810 reg_ctx->spspps_offset = reg_ctx->offset_spspps[i]; in hal_h265d_vdpu384a_gen_regs()
811 reg_ctx->sclst_offset = reg_ctx->offset_sclst[i]; in hal_h265d_vdpu384a_gen_regs()
813 reg_ctx->hw_regs = reg_ctx->g_buf[i].hw_regs; in hal_h265d_vdpu384a_gen_regs()
814 reg_ctx->g_buf[i].use_flag = 1; in hal_h265d_vdpu384a_gen_regs()
842 hw_regs = (Vdpu384aH265dRegSet*)reg_ctx->hw_regs; in hal_h265d_vdpu384a_gen_regs()
845 if (NULL == reg_ctx->hw_regs) { in hal_h265d_vdpu384a_gen_regs()
855 if (reg_ctx->cmv_bufs == NULL || reg_ctx->mv_size < mv_size) { in hal_h265d_vdpu384a_gen_regs()
858 if (reg_ctx->cmv_bufs) { in hal_h265d_vdpu384a_gen_regs()
859 hal_bufs_deinit(reg_ctx->cmv_bufs); in hal_h265d_vdpu384a_gen_regs()
860 reg_ctx->cmv_bufs = NULL; in hal_h265d_vdpu384a_gen_regs()
863 hal_bufs_init(®_ctx->cmv_bufs); in hal_h265d_vdpu384a_gen_regs()
864 if (reg_ctx->cmv_bufs == NULL) { in hal_h265d_vdpu384a_gen_regs()
869 reg_ctx->mv_size = mv_size; in hal_h265d_vdpu384a_gen_regs()
870 reg_ctx->mv_count = mpp_buf_slot_get_count(reg_ctx->slots); in hal_h265d_vdpu384a_gen_regs()
871 hal_bufs_setup(reg_ctx->cmv_bufs, reg_ctx->mv_count, 1, &size); in hal_h265d_vdpu384a_gen_regs()
881 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_ctx->pp.CurrPic.Index7Bits, in hal_h265d_vdpu384a_gen_regs()
885 reg_ctx->origin_bufs == NULL) { in hal_h265d_vdpu384a_gen_regs()
886 vdpu384a_setup_scale_origin_bufs(reg_ctx, mframe); in hal_h265d_vdpu384a_gen_regs()
943 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_ctx->pp.CurrPic.Index7Bits, in hal_h265d_vdpu384a_gen_regs()
946 if (reg_ctx->origin_bufs) { in hal_h265d_vdpu384a_gen_regs()
947 origin_buf = hal_bufs_get_buf(reg_ctx->origin_bufs, in hal_h265d_vdpu384a_gen_regs()
973 mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, dxva_ctx->pp.CurrPic.Index7Bits); in hal_h265d_vdpu384a_gen_regs()
986 mpp_buf_slot_get_prop(reg_ctx->packet_slots, syn->dec.input, SLOT_BUFFER, in hal_h265d_vdpu384a_gen_regs()
1006 mpp_dev_set_reg_offset(reg_ctx->dev, 130, mpp_buffer_get_size(streambuf)); in hal_h265d_vdpu384a_gen_regs()
1044 reg_ctx->error_index[syn->dec.reg_index] = dxva_ctx->pp.CurrPic.Index7Bits; in hal_h265d_vdpu384a_gen_regs()
1052 mpp_buf_slot_get_prop(reg_ctx->slots, in hal_h265d_vdpu384a_gen_regs()
1055 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_ctx->pp.RefPicList[i].Index7Bits, in hal_h265d_vdpu384a_gen_regs()
1058 origin_buf = hal_bufs_get_buf(reg_ctx->origin_bufs, in hal_h265d_vdpu384a_gen_regs()
1071 … reg_ctx->error_index[syn->dec.reg_index] = dxva_ctx->pp.RefPicList[i].Index7Bits; in hal_h265d_vdpu384a_gen_regs()
1079 mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, dxva_ctx->pp.RefPicList[i].Index7Bits); in hal_h265d_vdpu384a_gen_regs()
1084 if ((reg_ctx->error_index[syn->dec.reg_index] == dxva_ctx->pp.CurrPic.Index7Bits) && in hal_h265d_vdpu384a_gen_regs()
1092 hw_regs->common_addr.reg131_gbl_base = reg_ctx->bufs_fd; in hal_h265d_vdpu384a_gen_regs()
1095 mpp_dev_set_reg_offset(reg_ctx->dev, 131, reg_ctx->spspps_offset); in hal_h265d_vdpu384a_gen_regs()
1105 mpp_buf_slot_get_prop(reg_ctx->slots, in hal_h265d_vdpu384a_gen_regs()
1109 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_ctx->pp.RefPicList[i].Index7Bits, in hal_h265d_vdpu384a_gen_regs()
1113 … mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index[syn->dec.reg_index]); in hal_h265d_vdpu384a_gen_regs()
1119 mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index[syn->dec.reg_index]); in hal_h265d_vdpu384a_gen_regs()
1127 vdpu384a_setup_rcb(&hw_regs->common_addr, reg_ctx->dev, reg_ctx->fast_mode ? in hal_h265d_vdpu384a_gen_regs()
1128 reg_ctx->rcb_buf[syn->dec.reg_index] : reg_ctx->rcb_buf[0], in hal_h265d_vdpu384a_gen_regs()
1129 (Vdpu384aRcbInfo *)reg_ctx->rcb_info); in hal_h265d_vdpu384a_gen_regs()
1131 mpp_buffer_sync_end(reg_ctx->bufs); in hal_h265d_vdpu384a_gen_regs()
1139 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_ctx->pp.CurrPic.Index7Bits, in hal_h265d_vdpu384a_gen_regs()
1141 mpp_buf_slot_get_prop(reg_ctx->slots, dxva_ctx->pp.CurrPic.Index7Bits, in hal_h265d_vdpu384a_gen_regs()
1147 origin_buf = hal_bufs_get_buf(reg_ctx->origin_bufs, dxva_ctx->pp.CurrPic.Index7Bits); in hal_h265d_vdpu384a_gen_regs()
1155 …vdpu384a_setup_down_scale(mframe, reg_ctx->dev, &hw_regs->ctrl_regs, (void*)&hw_regs->h265d_paras); in hal_h265d_vdpu384a_gen_regs()
1159 …vdpu384a_setup_down_scale(mframe, reg_ctx->dev, &hw_regs->ctrl_regs, (void*)&hw_regs->h265d_paras); in hal_h265d_vdpu384a_gen_regs()
1176 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu384a_start() local
1182 (task->dec.flags.ref_err && !reg_ctx->cfg->base.disable_error)) { in hal_h265d_vdpu384a_start()
1187 if (reg_ctx->fast_mode) { in hal_h265d_vdpu384a_start()
1188 p = (RK_U8*)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu384a_start()
1189 hw_regs = ( Vdpu384aH265dRegSet *)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu384a_start()
1191 p = (RK_U8*)reg_ctx->hw_regs; in hal_h265d_vdpu384a_start()
1192 hw_regs = ( Vdpu384aH265dRegSet *)reg_ctx->hw_regs; in hal_h265d_vdpu384a_start()
1213 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu384a_start()
1222 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu384a_start()
1231 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu384a_start()
1240 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu384a_start()
1249 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_h265d_vdpu384a_start()
1256 vdpu384a_set_rcbinfo(reg_ctx->dev, (Vdpu384aRcbInfo*)reg_ctx->rcb_info); in hal_h265d_vdpu384a_start()
1258 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_CMD_SEND, NULL); in hal_h265d_vdpu384a_start()
1273 HalH265dCtx *reg_ctx = (HalH265dCtx *)hal; in hal_h265d_vdpu384a_wait() local
1278 if (reg_ctx->fast_mode) { in hal_h265d_vdpu384a_wait()
1279 hw_regs = ( Vdpu384aH265dRegSet *)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu384a_wait()
1281 hw_regs = ( Vdpu384aH265dRegSet *)reg_ctx->hw_regs; in hal_h265d_vdpu384a_wait()
1287 (task->dec.flags.ref_err && !reg_ctx->cfg->base.disable_error)) { in hal_h265d_vdpu384a_wait()
1292 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_CMD_POLL, NULL); in hal_h265d_vdpu384a_wait()
1306 if (!reg_ctx->fast_mode) { in hal_h265d_vdpu384a_wait()
1307 if (reg_ctx->dec_cb) in hal_h265d_vdpu384a_wait()
1308 mpp_callback(reg_ctx->dec_cb, &task->dec); in hal_h265d_vdpu384a_wait()
1311 mpp_buf_slot_get_prop(reg_ctx->slots, task->dec.output, in hal_h265d_vdpu384a_wait()
1314 reg_ctx->fast_mode_err_found = 1; in hal_h265d_vdpu384a_wait()
1319 if (reg_ctx->fast_mode && reg_ctx->fast_mode_err_found) { in hal_h265d_vdpu384a_wait()
1324 mpp_buf_slot_get_prop(reg_ctx->slots, task->dec.refer[i], in hal_h265d_vdpu384a_wait()
1330 mpp_buf_slot_get_prop(reg_ctx->slots, task->dec.output, in hal_h265d_vdpu384a_wait()
1353 if (reg_ctx->fast_mode) { in hal_h265d_vdpu384a_wait()
1354 reg_ctx->g_buf[index].use_flag = 0; in hal_h265d_vdpu384a_wait()