139     MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(VdpuAv1dRegCtx)));  in hal_av1d_alloc_res()
140     VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in hal_av1d_alloc_res()  local
144         reg_ctx->reg_buf[i].regs = mpp_calloc(VdpuAv1dRegSet, 1);  in hal_av1d_alloc_res()
145         memset(reg_ctx->reg_buf[i].regs, 0, sizeof(VdpuAv1dRegSet));  in hal_av1d_alloc_res()
149         reg_ctx->regs = reg_ctx->reg_buf[0].regs;  in hal_av1d_alloc_res()
152 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->prob_tbl_base, MPP_ALIGN(sizeof(AV1CDFs)…  in hal_av1d_alloc_res()
153 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->prob_tbl_out_base, MPP_ALIGN(sizeof(AV1C…  in hal_av1d_alloc_res()
154     BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->tile_info, AV1_TILE_INFO_SIZE));  in hal_av1d_alloc_res()
155 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->film_grain_mem, MPP_ALIGN(sizeof(AV1Film…  in hal_av1d_alloc_res()
156 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->global_model, MPP_ALIGN(GLOBAL_MODEL_SIZ…  in hal_av1d_alloc_res()
157 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->tile_buf, MPP_ALIGN(32 * MaxTiles, 4096)…  in hal_av1d_alloc_res()
235     VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in hal_av1d_release_res()  local
237     RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;  in hal_av1d_release_res()
240         MPP_FREE(reg_ctx->reg_buf[i].regs);  in hal_av1d_release_res()
242     BUF_PUT(reg_ctx->prob_tbl_base);  in hal_av1d_release_res()
243     BUF_PUT(reg_ctx->prob_tbl_out_base);  in hal_av1d_release_res()
244     BUF_PUT(reg_ctx->tile_info);  in hal_av1d_release_res()
245     BUF_PUT(reg_ctx->film_grain_mem);  in hal_av1d_release_res()
246     BUF_PUT(reg_ctx->global_model);  in hal_av1d_release_res()
247     BUF_PUT(reg_ctx->tile_buf);  in hal_av1d_release_res()
248     vdpu_av1d_filtermem_release(reg_ctx);  in hal_av1d_release_res()
249     hal_bufs_deinit(reg_ctx->tile_out_bufs);  in hal_av1d_release_res()
251     MPP_FREE(p_hal->reg_ctx);  in hal_av1d_release_res()
270         VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in vdpu_av1d_init()  local
272         reg_ctx->cdfs = &reg_ctx->default_cdfs;  in vdpu_av1d_init()
273         reg_ctx->cdfs_ndvc = &reg_ctx->default_cdfs_ndvc;  in vdpu_av1d_init()
274         reg_ctx->tile_transpose = 1;  in vdpu_av1d_init()
427     VdpuAv1dRegCtx *ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in set_ref_cb_base()
490     VdpuAv1dRegCtx *ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in set_ref_dbase()
738     VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in set_frame_sign_bias()  local
742             reg_ctx->ref_frame_sign_bias[i] = 0;  in set_frame_sign_bias()
752             reg_ctx->ref_frame_sign_bias[i + 1] = (rel_off <= 0) ? 0 : 1;  in set_frame_sign_bias()
761     VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in vdpu_av1d_set_prob()  local
763     void* prob_base = mpp_buffer_get_ptr(reg_ctx->prob_tbl_base);  in vdpu_av1d_set_prob()
764     VdpuAv1dRegSet *regs = reg_ctx->regs;  in vdpu_av1d_set_prob()
772     mpp_buffer_sync_end(reg_ctx->prob_tbl_base);  in vdpu_av1d_set_prob()
774 …regs->addr_cfg.swreg171.sw_prob_tab_out_base_lsb    = mpp_buffer_get_fd(reg_ctx->prob_tbl_out_base…  in vdpu_av1d_set_prob()
775     regs->addr_cfg.swreg173.sw_prob_tab_base_lsb        = mpp_buffer_get_fd(reg_ctx->prob_tbl_base);  in vdpu_av1d_set_prob()
1112     VdpuAv1dRegCtx *ctx = p_hal->reg_ctx;  in vdpu_av1d_superres_params()
1215     VdpuAv1dRegCtx *ctx = p_hal->reg_ctx;  in vdpu_av1d_set_picture_dimensions()
1395     VdpuAv1dRegCtx *ctx = p_hal->reg_ctx;  in vdpu_av1d_set_loopfilter()
1431     VdpuAv1dRegCtx *ctx = p_hal->reg_ctx;  in vdpu_av1d_set_global_model()
1522     VdpuAv1dRegCtx *ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in vdpu_av1d_set_tile_info_mem()
1616     VdpuAv1dRegCtx *ctx = p_hal->reg_ctx;  in vdpu_av1d_set_cdef()
1644     VdpuAv1dRegCtx *ctx = p_hal->reg_ctx;  in vdpu_av1d_set_lr()
1821     VdpuAv1dRegCtx *ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in vdpu_av1d_setup_tile_bufs()
1857     VdpuAv1dRegCtx *ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in vdpu_av1d_gen_regs()
2247     VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in vdpu_av1d_start()  local
2249                            reg_ctx->reg_buf[task->dec.reg_index].regs :  in vdpu_av1d_start()
2250                            reg_ctx->regs;  in vdpu_av1d_start()
2309     VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in vdpu_av1d_wait()  local
2311                              reg_ctx->reg_buf[task->dec.reg_index].regs :  in vdpu_av1d_wait()
2312                              reg_ctx->regs;  in vdpu_av1d_wait()
2343         RK_U32 *prob_out = (RK_U32*)mpp_buffer_get_ptr(reg_ctx->prob_tbl_out_base);  in vdpu_av1d_wait()
2345         mpp_buffer_sync_ro_begin(reg_ctx->prob_tbl_out_base);  in vdpu_av1d_wait()
2346         m_ctx.task = mpp_buffer_get_ptr(reg_ctx->prob_tbl_out_base);//(void *)&task->dec;  in vdpu_av1d_wait()
2356         reg_ctx->reg_buf[task->dec.reg_index].valid = 0;  in vdpu_av1d_wait()