423         H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;  in vdpu1_set_vlc_regs()  local
424         RK_U32 *pocBase = (RK_U32 *)reg_ctx->poc_ptr;  in vdpu1_set_vlc_regs()
651         H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;  in vdpu1_set_asic_regs()  local
654             RK_U32 *ptr = (RK_U32 *)reg_ctx->sclst_ptr;  in vdpu1_set_asic_regs()
676         p_regs->SwReg40.qtable_st_adr = mpp_buffer_get_fd(reg_ctx->buf);  in vdpu1_set_asic_regs()
752     MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(H264dVdpuRegCtx_t)));  in vdpu1_h264d_init()
753     H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;  in vdpu1_h264d_init()  local
757         RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;  in vdpu1_h264d_init()
761             FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, &reg_ctx->reg_buf[i].buf,  buf_size));  in vdpu1_h264d_init()
762             reg_ctx->reg_buf[i].cabac_ptr = mpp_buffer_get_ptr(reg_ctx->reg_buf[i].buf);  in vdpu1_h264d_init()
763             reg_ctx->reg_buf[i].poc_ptr = reg_ctx->reg_buf[i].cabac_ptr + VDPU_CABAC_TAB_SIZE;  in vdpu1_h264d_init()
764             reg_ctx->reg_buf[i].sclst_ptr = reg_ctx->reg_buf[i].poc_ptr + VDPU_POC_BUF_SIZE;  in vdpu1_h264d_init()
765             reg_ctx->reg_buf[i].regs = mpp_calloc_size(void, sizeof(H264dVdpu1Regs_t));  in vdpu1_h264d_init()
767 …        memcpy(reg_ctx->reg_buf[i].cabac_ptr, (void *)vdpu_cabac_table,  sizeof(vdpu_cabac_table));  in vdpu1_h264d_init()
771         reg_ctx->buf = reg_ctx->reg_buf[0].buf;  in vdpu1_h264d_init()
772         reg_ctx->cabac_ptr = reg_ctx->reg_buf[0].cabac_ptr;  in vdpu1_h264d_init()
773         reg_ctx->poc_ptr = reg_ctx->reg_buf[0].poc_ptr;  in vdpu1_h264d_init()
774         reg_ctx->sclst_ptr = reg_ctx->reg_buf[0].sclst_ptr;  in vdpu1_h264d_init()
775         reg_ctx->regs = reg_ctx->reg_buf[0].regs;  in vdpu1_h264d_init()
799     H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;  in vdpu1_h264d_deinit()  local
802     RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;  in vdpu1_h264d_deinit()
804         MPP_FREE(reg_ctx->reg_buf[i].regs);  in vdpu1_h264d_deinit()
805         mpp_buffer_put(reg_ctx->reg_buf[i].buf);  in vdpu1_h264d_deinit()
807     MPP_FREE(p_hal->reg_ctx);  in vdpu1_h264d_deinit()
835     H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;  in vdpu1_h264d_gen_regs()  local
838         for (i = 0; i <  MPP_ARRAY_ELEMS(reg_ctx->reg_buf); i++) {  in vdpu1_h264d_gen_regs()
839             if (!reg_ctx->reg_buf[i].valid) {  in vdpu1_h264d_gen_regs()
841                 reg_ctx->buf = reg_ctx->reg_buf[i].buf;  in vdpu1_h264d_gen_regs()
842                 reg_ctx->cabac_ptr = reg_ctx->reg_buf[i].cabac_ptr;  in vdpu1_h264d_gen_regs()
843                 reg_ctx->poc_ptr = reg_ctx->reg_buf[i].poc_ptr;  in vdpu1_h264d_gen_regs()
844                 reg_ctx->sclst_ptr = reg_ctx->reg_buf[i].sclst_ptr;  in vdpu1_h264d_gen_regs()
845                 reg_ctx->regs = reg_ctx->reg_buf[i].regs;  in vdpu1_h264d_gen_regs()
846                 reg_ctx->reg_buf[i].valid = 1;  in vdpu1_h264d_gen_regs()
853     FUN_CHECK(ret = vdpu1_set_device_regs(p_hal, (H264dVdpu1Regs_t *)reg_ctx->regs));  in vdpu1_h264d_gen_regs()
854     FUN_CHECK(ret = vdpu1_set_pic_regs(p_hal, (H264dVdpu1Regs_t *)reg_ctx->regs));  in vdpu1_h264d_gen_regs()
855     FUN_CHECK(ret = vdpu1_set_vlc_regs(p_hal, (H264dVdpu1Regs_t *)reg_ctx->regs));  in vdpu1_h264d_gen_regs()
856     FUN_CHECK(ret = vdpu1_set_ref_regs(p_hal, (H264dVdpu1Regs_t *)reg_ctx->regs));  in vdpu1_h264d_gen_regs()
857     FUN_CHECK(ret = vdpu1_set_asic_regs(p_hal, (H264dVdpu1Regs_t *)reg_ctx->regs));  in vdpu1_h264d_gen_regs()
858     mpp_buffer_sync_end(reg_ctx->buf);  in vdpu1_h264d_gen_regs()
877     H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;  in vdpu1_h264d_start()  local
879                                                     reg_ctx->reg_buf[task->dec.reg_index].regs :  in vdpu1_h264d_start()
880                                                     reg_ctx->regs);  in vdpu1_h264d_start()
899         wr_cfg.reg = reg_ctx->regs;  in vdpu1_h264d_start()
909         rd_cfg.reg = reg_ctx->regs;  in vdpu1_h264d_start()
942     H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;  in vdpu1_h264d_wait()  local
944                                                     reg_ctx->reg_buf[task->dec.reg_index].regs :  in vdpu1_h264d_wait()
945                                                     reg_ctx->regs);  in vdpu1_h264d_wait()
961         param.regs = (RK_U32 *)reg_ctx->regs;  in vdpu1_h264d_wait()
968         reg_ctx->reg_buf[task->dec.reg_index].valid = 0;  in vdpu1_h264d_wait()