1 /*
2 *
3 * Copyright 2015 Rockchip Electronics Co. LTD
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
17
18 #define MODULE_TAG "hal_h264d_vdpu_reg"
19
20 #include <stdio.h>
21 #include <stdlib.h>
22 #include <string.h>
23
24 #include "rk_type.h"
25 #include "mpp_err.h"
26 #include "mpp_mem.h"
27 #include "mpp_soc.h"
28 #include "mpp_common.h"
29
30 #include "hal_h264d_global.h"
31 #include "hal_h264d_api.h"
32 #include "hal_h264d_vdpu_com.h"
33 #include "hal_h264d_vdpu2.h"
34 #include "hal_h264d_vdpu2_reg.h"
35 #include "mpp_dec_cb_param.h"
36
37 const RK_U32 vdpu2_ref_idx[16] = {
38 84, 85, 86, 87, 88, 89, 90, 91,
39 92, 93, 94, 95, 96, 97, 98, 99
40 };
41
42 MPP_RET vdpu2_h264d_deinit(void *hal);
set_device_regs(H264dHalCtx_t * p_hal,H264dVdpuRegs_t * p_reg)43 static MPP_RET set_device_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_reg)
44 {
45 MPP_RET ret = MPP_ERR_UNKNOW;
46
47 p_reg->sw53.dec_fmt_sel = 0; //!< set H264 mode
48 p_reg->sw54.dec_out_endian = 1; //!< little endian
49 p_reg->sw54.dec_in_endian = 0; //!< big endian
50 p_reg->sw54.dec_strendian_e = 1; //!< little endian
51 p_reg->sw50.dec_tiled_msb = 0; //!< 0: raster scan 1: tiled
52 p_reg->sw56.dec_max_burlen = 16; //!< (0, 4, 8, 16) choice one
53 p_reg->sw50.dec_ascmd0_dis = 0; //!< disable
54 p_reg->sw50.adv_pref_dis = 0; //!< disable
55 p_reg->sw52.adv_pref_thrd = 8;
56 p_reg->sw50.adtion_latency = 0; //!< compensation for bus latency; values up to 63
57 p_reg->sw56.dec_data_discd_en = 0;
58 p_reg->sw54.dec_out_wordsp = 1;//!< little endian
59 p_reg->sw54.dec_in_wordsp = 1;//!< little endian
60 p_reg->sw54.dec_strm_wordsp = 1;//!< little endian
61 p_reg->sw57.timeout_sts_en = 1;
62 p_reg->sw57.dec_clkgate_en = 1;
63 p_reg->sw55.dec_irq_dis = 0;
64 //!< set AXI RW IDs
65 p_reg->sw56.dec_axi_id_rd = (0xFF & 0xFFU); //!< 0-255
66 p_reg->sw56.dec_axi_id_wr = (0x0 & 0xFFU); //!< 0-255
67 ///!< Set prediction filter taps
68 {
69 RK_U32 val = 0;
70 p_reg->sw59.pflt_set0_tap0 = 1;
71 val = (RK_U32)(-5);
72 p_reg->sw59.pflt_set0_tap1 = val;
73 p_reg->sw59.pflt_set0_tap2 = 20;
74 }
75 p_reg->sw50.adtion_latency = 0;
76 //!< clock_gating 0:clock always on, 1: clock gating module control the key(turn off when decoder free)
77 p_reg->sw57.dec_clkgate_en = 1;
78 p_reg->sw50.dec_tiled_msb = 0; //!< 0: raster scan 1: tiled
79 //!< bus_burst_length = 16, bus burst
80 p_reg->sw56.dec_max_burlen = 16;
81 p_reg->sw56.dec_data_discd_en = 0;
82 (void)p_hal;
83
84 return ret = MPP_OK;
85 }
86
set_refer_pic_idx(H264dVdpuRegs_t * p_regs,RK_U32 i,RK_U16 val)87 static MPP_RET set_refer_pic_idx(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 val)
88 {
89 switch (i) {
90 case 0:
91 p_regs->sw76.num_ref_idx0 = val;
92 break;
93 case 1:
94 p_regs->sw76.num_ref_idx1 = val;
95 break;
96 case 2:
97 p_regs->sw77.num_ref_idx2 = val;
98 break;
99 case 3:
100 p_regs->sw77.num_ref_idx3 = val;
101 break;
102 case 4:
103 p_regs->sw78.num_ref_idx4 = val;
104 break;
105 case 5:
106 p_regs->sw78.num_ref_idx5 = val;
107 break;
108 case 6:
109 p_regs->sw79.num_ref_idx6 = val;
110 break;
111 case 7:
112 p_regs->sw79.num_ref_idx7 = val;
113 break;
114 case 8:
115 p_regs->sw80.num_ref_idx8 = val;
116 break;
117 case 9:
118 p_regs->sw80.num_ref_idx9 = val;
119 break;
120 case 10:
121 p_regs->sw81.num_ref_idx10 = val;
122 break;
123 case 11:
124 p_regs->sw81.num_ref_idx11 = val;
125 break;
126 case 12:
127 p_regs->sw82.num_ref_idx12 = val;
128 break;
129 case 13:
130 p_regs->sw82.num_ref_idx13 = val;
131 break;
132 case 14:
133 p_regs->sw83.num_ref_idx14 = val;
134 break;
135 case 15:
136 p_regs->sw83.num_ref_idx15 = val;
137 break;
138 default:
139 break;
140 }
141
142 return MPP_OK;
143 }
144
set_refer_pic_list_p(H264dVdpuRegs_t * p_regs,RK_U32 i,RK_U16 val)145 static MPP_RET set_refer_pic_list_p(H264dVdpuRegs_t *p_regs, RK_U32 i,
146 RK_U16 val)
147 {
148 switch (i) {
149 case 0:
150 p_regs->sw106.init_reflist_pf0 = val;
151 break;
152 case 1:
153 p_regs->sw106.init_reflist_pf1 = val;
154 break;
155 case 2:
156 p_regs->sw106.init_reflist_pf2 = val;
157 break;
158 case 3:
159 p_regs->sw106.init_reflist_pf3 = val;
160 break;
161 case 4:
162 p_regs->sw74.init_reflist_pf4 = val;
163 break;
164 case 5:
165 p_regs->sw74.init_reflist_pf5 = val;
166 break;
167 case 6:
168 p_regs->sw74.init_reflist_pf6 = val;
169 break;
170 case 7:
171 p_regs->sw74.init_reflist_pf7 = val;
172 break;
173 case 8:
174 p_regs->sw74.init_reflist_pf8 = val;
175 break;
176 case 9:
177 p_regs->sw74.init_reflist_pf9 = val;
178 break;
179 case 10:
180 p_regs->sw75.init_reflist_pf10 = val;
181 break;
182 case 11:
183 p_regs->sw75.init_reflist_pf11 = val;
184 break;
185 case 12:
186 p_regs->sw75.init_reflist_pf12 = val;
187 break;
188 case 13:
189 p_regs->sw75.init_reflist_pf13 = val;
190 break;
191 case 14:
192 p_regs->sw75.init_reflist_pf14 = val;
193 break;
194 case 15:
195 p_regs->sw75.init_reflist_pf15 = val;
196 break;
197 default:
198 break;
199 }
200
201 return MPP_OK;
202 }
203
set_refer_pic_list_b0(H264dVdpuRegs_t * p_regs,RK_U32 i,RK_U16 val)204 static MPP_RET set_refer_pic_list_b0(H264dVdpuRegs_t *p_regs, RK_U32 i,
205 RK_U16 val)
206 {
207 switch (i) {
208 case 0:
209 p_regs->sw100.init_reflist_df0 = val;
210 break;
211 case 1:
212 p_regs->sw100.init_reflist_df1 = val;
213 break;
214 case 2:
215 p_regs->sw100.init_reflist_df2 = val;
216 break;
217 case 3:
218 p_regs->sw100.init_reflist_df3 = val;
219 break;
220 case 4:
221 p_regs->sw100.init_reflist_df4 = val;
222 break;
223 case 5:
224 p_regs->sw100.init_reflist_df5 = val;
225 break;
226 case 6:
227 p_regs->sw101.init_reflist_df6 = val;
228 break;
229 case 7:
230 p_regs->sw101.init_reflist_df7 = val;
231 break;
232 case 8:
233 p_regs->sw101.init_reflist_df8 = val;
234 break;
235 case 9:
236 p_regs->sw101.init_reflist_df9 = val;
237 break;
238 case 10:
239 p_regs->sw101.init_reflist_df10 = val;
240 break;
241 case 11:
242 p_regs->sw101.init_reflist_df11 = val;
243 break;
244 case 12:
245 p_regs->sw102.init_reflist_df12 = val;
246 break;
247 case 13:
248 p_regs->sw102.init_reflist_df13 = val;
249 break;
250 case 14:
251 p_regs->sw102.init_reflist_df14 = val;
252 break;
253 case 15:
254 p_regs->sw102.init_reflist_df15 = val;
255 break;
256 default:
257 break;
258 }
259
260 return MPP_OK;
261 }
262
set_refer_pic_list_b1(H264dVdpuRegs_t * p_regs,RK_U32 i,RK_U16 val)263 static MPP_RET set_refer_pic_list_b1(H264dVdpuRegs_t *p_regs, RK_U32 i,
264 RK_U16 val)
265 {
266 switch (i) {
267 case 0:
268 p_regs->sw103.init_reflist_db0 = val;
269 break;
270 case 1:
271 p_regs->sw103.init_reflist_db1 = val;
272 break;
273 case 2:
274 p_regs->sw103.init_reflist_db2 = val;
275 break;
276 case 3:
277 p_regs->sw103.init_reflist_db3 = val;
278 break;
279 case 4:
280 p_regs->sw103.init_reflist_db4 = val;
281 break;
282 case 5:
283 p_regs->sw103.init_reflist_db5 = val;
284 break;
285 case 6:
286 p_regs->sw104.init_reflist_db6 = val;
287 break;
288 case 7:
289 p_regs->sw104.init_reflist_db7 = val;
290 break;
291 case 8:
292 p_regs->sw104.init_reflist_db8 = val;
293 break;
294 case 9:
295 p_regs->sw104.init_reflist_db9 = val;
296 break;
297 case 10:
298 p_regs->sw104.init_reflist_db10 = val;
299 break;
300 case 11:
301 p_regs->sw104.init_reflist_db11 = val;
302 break;
303 case 12:
304 p_regs->sw105.init_reflist_db12 = val;
305 break;
306 case 13:
307 p_regs->sw105.init_reflist_db13 = val;
308 break;
309 case 14:
310 p_regs->sw105.init_reflist_db14 = val;
311 break;
312 case 15:
313 p_regs->sw105.init_reflist_db15 = val;
314 break;
315 default:
316 break;
317 }
318
319 return MPP_OK;
320 }
321
set_refer_pic_base_addr(H264dVdpuRegs_t * p_regs,RK_U32 i,RK_U32 val)322 static MPP_RET set_refer_pic_base_addr(H264dVdpuRegs_t *p_regs, RK_U32 i,
323 RK_U32 val)
324 {
325 switch (i) {
326 case 0:
327 p_regs->sw84.ref0_st_addr = val;
328 break;
329 case 1:
330 p_regs->sw85.ref1_st_addr = val;
331 break;
332 case 2:
333 p_regs->sw86.ref2_st_addr = val;
334 break;
335 case 3:
336 p_regs->sw87.ref3_st_addr = val;
337 break;
338 case 4:
339 p_regs->sw88.ref4_st_addr = val;
340 break;
341 case 5:
342 p_regs->sw89.ref5_st_addr = val;
343 break;
344 case 6:
345 p_regs->sw90.ref6_st_addr = val;
346 break;
347 case 7:
348 p_regs->sw91.ref7_st_addr = val;
349 break;
350 case 8:
351 p_regs->sw92.ref8_st_addr = val;
352 break;
353 case 9:
354 p_regs->sw93.ref9_st_addr = val;
355 break;
356 case 10:
357 p_regs->sw94.ref10_st_addr = val;
358 break;
359 case 11:
360 p_regs->sw95.ref11_st_addr = val;
361 break;
362 case 12:
363 p_regs->sw96.ref12_st_addr = val;
364 break;
365 case 13:
366 p_regs->sw97.ref13_st_addr = val;
367 break;
368 case 14:
369 p_regs->sw98.ref14_st_addr = val;
370 break;
371 case 15:
372 p_regs->sw99.ref15_st_addr = val;
373 break;
374 default:
375 break;
376 }
377 return MPP_OK;
378 }
379
set_pic_regs(H264dHalCtx_t * p_hal,H264dVdpuRegs_t * p_regs)380 static MPP_RET set_pic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
381 {
382 MPP_RET ret = MPP_ERR_UNKNOW;
383
384 p_regs->sw110.pic_mb_w = p_hal->pp->wFrameWidthInMbsMinus1 + 1;
385 p_regs->sw110.pic_mb_h = (2 - p_hal->pp->frame_mbs_only_flag)
386 * (p_hal->pp->wFrameHeightInMbsMinus1 + 1);
387
388 return ret = MPP_OK;
389 }
390
set_vlc_regs(H264dHalCtx_t * p_hal,H264dVdpuRegs_t * p_regs)391 static MPP_RET set_vlc_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
392 {
393 RK_U32 i = 0;
394 MPP_RET ret = MPP_ERR_UNKNOW;
395 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
396 RK_U32 validFlags = 0;
397 RK_U32 longTermTmp = 0, longTermflags = 0;
398
399 p_regs->sw57.dec_wr_extmen_dis = 0;
400 p_regs->sw57.rlc_mode_en = 0;
401 p_regs->sw51.qp_init_val = pp->pic_init_qp_minus26 + 26;
402 p_regs->sw114.max_refidx0 = pp->num_ref_idx_l0_active_minus1 + 1;
403 p_regs->sw111.max_refnum = pp->num_ref_frames;
404 p_regs->sw112.cur_frm_len = pp->log2_max_frame_num_minus4 + 4;
405 p_regs->sw112.curfrm_num = pp->frame_num;
406 p_regs->sw115.const_intra_en = pp->constrained_intra_pred_flag;
407 p_regs->sw112.dblk_ctrl_flag = pp->deblocking_filter_control_present_flag;
408 p_regs->sw112.rpcp_flag = pp->redundant_pic_cnt_present_flag;
409 p_regs->sw113.refpic_mk_len = p_hal->slice_long[0].drpm_used_bitlen;
410 p_regs->sw115.idr_pic_flag = p_hal->slice_long[0].idr_flag;
411 p_regs->sw113.idr_pic_id = p_hal->slice_long[0].idr_pic_id;
412 p_regs->sw114.pps_id = p_hal->slice_long[0].active_pps_id;
413 p_regs->sw114.poc_field_len = p_hal->slice_long[0].poc_used_bitlen;
414 /* reference picture flags, TODO separate fields */
415 if (pp->field_pic_flag) {
416 for (i = 0; i < 32; i++) {
417 if (pp->RefFrameList[i / 2].bPicEntry == 0xff) { //!< invalid
418 longTermflags <<= 1;
419 validFlags <<= 1;
420 } else {
421 longTermTmp = pp->RefFrameList[i / 2].AssociatedFlag; //!< get long term flag
422 longTermflags = (longTermflags << 1) | longTermTmp;
423
424 validFlags = (validFlags << 1)
425 | ((pp->UsedForReferenceFlags >> i) & 0x01);
426 }
427 }
428 p_regs->sw107.refpic_term_flag = longTermflags;
429 p_regs->sw108.refpic_valid_flag = validFlags;
430 } else {
431 for (i = 0; i < 16; i++) {
432 if (pp->RefFrameList[i].bPicEntry == 0xff) { //!< invalid
433 longTermflags <<= 1;
434 validFlags <<= 1;
435 } else {
436 RK_U32 use_flag = (pp->UsedForReferenceFlags >> (2 * i)) & 0x03;
437
438 longTermTmp = pp->RefFrameList[i].AssociatedFlag;
439 longTermflags = (longTermflags << 1) | longTermTmp;
440 validFlags = (validFlags << 1) | (use_flag > 0);
441 }
442 }
443 p_regs->sw107.refpic_term_flag = (longTermflags << 16);
444 p_regs->sw108.refpic_valid_flag = (validFlags << 16);
445 }
446
447 for (i = 0; i < 16; i++) {
448 if (pp->RefFrameList[i].bPicEntry != 0xff) { //!< valid
449 if (pp->RefFrameList[i].AssociatedFlag) { //!< longterm flag
450 set_refer_pic_idx(p_regs, i, pp->LongTermPicNumList[i]); //!< pic_num
451 } else {
452 set_refer_pic_idx(p_regs, i, pp->FrameNumList[i]); //< frame_num
453 }
454 }
455 }
456 p_regs->sw57.rd_cnt_tab_en = 1;
457 //!< set poc to buffer
458 {
459 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
460 RK_U32 *ptr = (RK_U32 *)reg_ctx->poc_ptr;
461
462 //!< set reference reorder poc
463 for (i = 0; i < 32; i++) {
464 if (pp->RefFrameList[i / 2].bPicEntry != 0xff) {
465 *ptr++ = pp->FieldOrderCntList[i / 2][i & 0x1];
466 } else {
467 *ptr++ = 0;
468 }
469 }
470 //!< set current poc
471 if (pp->field_pic_flag || !pp->MbaffFrameFlag) {
472 if (pp->field_pic_flag)
473 *ptr++ = pp->CurrFieldOrderCnt[pp->CurrPic.AssociatedFlag ? 1 : 0];
474 else
475 *ptr++ = MPP_MIN(pp->CurrFieldOrderCnt[0], pp->CurrFieldOrderCnt[1]);
476 } else {
477 *ptr++ = pp->CurrFieldOrderCnt[0];
478 *ptr++ = pp->CurrFieldOrderCnt[1];
479 }
480
481 #if DEBUG_REF_LIST
482 {
483 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
484 RK_U32 *ptr_tmp = (RK_U32 *)reg_ctx->poc_ptr;
485 RK_U32 *ref_reg = &p_regs->sw76;
486 char file_name[128];
487 sprintf(file_name, "/sdcard/test/mpp_pocbase_log.txt");
488 FILE *fp = fopen(file_name, "ab");
489 char buf[1024];
490 RK_S32 buf_len = 0, buf_size = sizeof(buf) - 1;
491
492 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "=== poc_base filed %d fram_num %d ===\n",
493 pp->field_pic_flag || !pp->MbaffFrameFlag, pp->frame_num);
494 for (; ptr_tmp < ptr; ptr_tmp++)
495 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "poc 0x%08x\n", *ptr_tmp);
496 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "term_flag 0x%08x refpic_valid_flag 0x%08x \n",
497 longTermflags, validFlags);
498 for (i = 0; i < 8; i++)
499 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "ref[%d] 0x%08x\n", i, ref_reg[i]);
500 fprintf(fp, "%s", buf);
501
502 fflush(fp);
503 fclose(fp);
504 }
505 #endif
506 }
507 p_regs->sw115.cabac_en = pp->entropy_coding_mode_flag;
508 //!< stream position update
509 {
510 MppBuffer bitstream_buf = NULL;
511 p_regs->sw57.st_code_exit = 1;
512 mpp_buf_slot_get_prop(p_hal->packet_slots,
513 p_hal->in_task->input,
514 SLOT_BUFFER, &bitstream_buf);
515 p_regs->sw109.strm_start_bit = 0; //!< sodb stream start bit
516 p_regs->sw64.rlc_vlc_st_adr = mpp_buffer_get_fd(bitstream_buf);
517 p_regs->sw51.stream_len = p_hal->strm_len;
518 }
519
520 return ret = MPP_OK;
521 }
522
set_ref_regs(H264dHalCtx_t * p_hal,H264dVdpuRegs_t * p_regs)523 static MPP_RET set_ref_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
524 {
525 MPP_RET ret = MPP_ERR_UNKNOW;
526 RK_U32 i = 0;
527 RK_U32 num_refs = 0;
528 RK_U32 num_reorder = 0;
529 H264dRefsList_t m_lists[3][16];
530 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
531 RK_U32 max_frame_num = 1 << (pp->log2_max_frame_num_minus4 + 4);
532
533 // init list
534 memset(m_lists, 0, sizeof(m_lists));
535 for (i = 0; i < 16; i++) {
536 RK_U32 ref_flag = pp->UsedForReferenceFlags >> (2 * i) & 0x3;
537
538 m_lists[0][i].idx = i;
539 if (ref_flag) {
540 num_refs++;
541 m_lists[0][i].cur_poc = pp->CurrPic.AssociatedFlag
542 ? pp->CurrFieldOrderCnt[1] : pp->CurrFieldOrderCnt[0];
543 m_lists[0][i].ref_flag = ref_flag;
544 m_lists[0][i].lt_flag = pp->RefFrameList[i].AssociatedFlag;
545 if (m_lists[0][i].lt_flag) {
546 m_lists[0][i].ref_picnum = pp->LongTermPicNumList[i];
547 } else {
548 m_lists[0][i].ref_picnum = pp->FrameNumList[i] > pp->frame_num ?
549 (pp->FrameNumList[i] - max_frame_num) :
550 pp->FrameNumList[i];
551 }
552
553 if (ref_flag == 3) {
554 m_lists[0][i].ref_poc = MPP_MIN(pp->FieldOrderCntList[i][0], pp->FieldOrderCntList[i][1]);
555 } else if (ref_flag & 0x1) {
556 m_lists[0][i].ref_poc = pp->FieldOrderCntList[i][0];
557 } else if (ref_flag & 0x2) {
558 m_lists[0][i].ref_poc = pp->FieldOrderCntList[i][1];
559 }
560 #if DEBUG_REF_LIST
561 mpp_log("i %d ref_pic_num %d lt_flag %d ref_flag %d ref_poc %d cur_poc %d\n",
562 i, m_lists[0][i].ref_picnum, m_lists[0][i].lt_flag, ref_flag,
563 m_lists[0][i].ref_poc, m_lists[0][i].cur_poc);
564 #endif
565 num_reorder = i + 1;
566 }
567 }
568 /*
569 * the value of num_reorder may be greater than num_refs,
570 * e.g. v: valid x: invalid
571 * num_refs = 3, num_reorder = 4
572 * the index 1 will be reorder to the end
573 * ┌─┬─┬─┬─┬─┬─┬─┐
574 * │0│1│2│3│.│.│F│
575 * ├─┼─┼─┼─┼─┼─┼─┤
576 * │v│x│v│v│x│x│x│
577 * └─┴─┴─┴─┴─┴─┴─┘
578 */
579 memcpy(m_lists[1], m_lists[0], sizeof(m_lists[0]));
580 memcpy(m_lists[2], m_lists[0], sizeof(m_lists[0]));
581 qsort(m_lists[0], num_reorder, sizeof(m_lists[0][0]), compare_p);
582 qsort(m_lists[1], num_reorder, sizeof(m_lists[1][0]), compare_b0);
583 qsort(m_lists[2], num_reorder, sizeof(m_lists[2][0]), compare_b1);
584 if (num_refs > 1 && !p_hal->pp->field_pic_flag) {
585 if (!memcmp(m_lists[1], m_lists[2], sizeof(m_lists[1]))) {
586 MPP_SWAP(H264dRefsList_t, m_lists[2][0], m_lists[2][1]);
587 }
588 }
589
590 //!< list0 list1 listP
591 for (i = 0; i < 16; i++) {
592 set_refer_pic_list_p(p_regs, i, m_lists[0][i].idx);
593 set_refer_pic_list_b0(p_regs, i, m_lists[1][i].idx);
594 set_refer_pic_list_b1(p_regs, i, m_lists[2][i].idx);
595 }
596 #if DEBUG_REF_LIST
597 {
598 char file_name[128]; \
599 sprintf(file_name, "/sdcard/test/mpp2_RefPicList_log.txt"); \
600 FILE *fp = fopen(file_name, "ab"); \
601 char buf[1024];
602 RK_S32 buf_len = 0, buf_size = sizeof(buf) - 1;
603 // fwrite(buf, 1, size, fp);
604 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "frame_num %d field %d bottom %d\n",
605 pp->frame_num, pp->field_pic_flag, pp->CurrPic.AssociatedFlag);
606 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "list0 : ");
607 for (i = 0; i < 16; i++)
608 buf_len += snprintf(buf + buf_len, buf_size - buf_len, " %04d", m_lists[1][i]);
609 fprintf(fp, "%s\n", buf);
610
611 buf_len = 0;
612 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "list1 : ");
613 for (i = 0; i < 16; i++)
614 buf_len += snprintf(buf + buf_len, buf_size - buf_len, " %04d", m_lists[2][i]);
615 fprintf(fp, "%s\n", buf);
616
617 buf_len = 0;
618 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "listP : ");
619 for (i = 0; i < 16; i++)
620 buf_len += snprintf(buf + buf_len, buf_size - buf_len, " %04d", m_lists[0][i]);
621 fprintf(fp, "%s\n", buf);
622
623 fflush(fp); \
624 fclose(fp); \
625 }
626 #endif
627
628 return ret = MPP_OK;
629 }
630
set_asic_regs(H264dHalCtx_t * p_hal,H264dVdpuRegs_t * p_regs)631 static MPP_RET set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
632 {
633 RK_U32 i = 0, j = 0;
634 RK_U32 outPhyAddr = 0;
635 MppBuffer frame_buf = NULL;
636 MPP_RET ret = MPP_ERR_UNKNOW;
637 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
638 DXVA_Slice_H264_Long *p_long = &p_hal->slice_long[0];
639
640 {
641 #if DEBUG_REF_LIST
642 char file_name[128]; \
643 sprintf(file_name, "/sdcard/test/mpp2_dpb_log.txt"); \
644 FILE *fp = fopen(file_name, "ab"); \
645 char buf[2048];
646 static RK_U32 num = 0;
647 RK_S32 buf_len = 0, buf_size = sizeof(buf) - 1;
648
649 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "cnt %d frame_num %d field %d bottom %d\n",
650 num++, pp->frame_num, pp->field_pic_flag, pp->CurrPic.AssociatedFlag);
651 #endif
652 for (i = 0, j = 0xff; i < MPP_ARRAY_ELEMS(pp->RefFrameList); i++) {
653 RK_U32 val = 0;
654 RK_U32 top_closer = 0;
655 RK_U32 field_flag = 0;
656 RK_S32 cur_poc = 0;
657 RK_U32 used_flag = 0;
658
659 if (pp->RefFrameList[i].bPicEntry != 0xff) {
660 mpp_buf_slot_get_prop(p_hal->frame_slots,
661 pp->RefFrameList[i].Index7Bits,
662 SLOT_BUFFER, &frame_buf); //!< reference phy addr
663 j = i;
664 #if DEBUG_REF_LIST
665 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "refPicList[%d], frame_num=%d, poc0=%d, poc1=%d\n",
666 i, pp->FrameNumList[i], pp->FieldOrderCntList[i][0], pp->FieldOrderCntList[i][1]);
667 #endif
668 } else {
669 mpp_buf_slot_get_prop(p_hal->frame_slots,
670 pp->CurrPic.Index7Bits,
671 SLOT_BUFFER, &frame_buf); //!< current out phy addr
672 }
673
674 field_flag = ((pp->RefPicFiledFlags >> i) & 0x1) ? 0x2 : 0;
675 cur_poc = pp->CurrPic.AssociatedFlag
676 ? pp->CurrFieldOrderCnt[1] : pp->CurrFieldOrderCnt[0];
677 used_flag = ((pp->UsedForReferenceFlags >> (2 * i)) & 0x3);
678 if (used_flag & 0x3) {
679 top_closer = MPP_ABS(pp->FieldOrderCntList[i][0] - cur_poc) <
680 MPP_ABS(pp->FieldOrderCntList[i][1] - cur_poc) ? 0x1 : 0;
681 } else if (used_flag & 0x2) {
682 top_closer = 0;
683 } else if (used_flag & 0x1) {
684 top_closer = 1;
685 }
686 val = top_closer | field_flag;
687 if (val) {
688 mpp_dev_set_reg_offset(p_hal->dev, vdpu2_ref_idx[i], val);
689 #if DEBUG_REF_LIST
690 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "ref_offset[%d] %d\n",
691 i, val);
692 #endif
693 }
694 set_refer_pic_base_addr(p_regs, i, mpp_buffer_get_fd(frame_buf));
695 }
696 #if DEBUG_REF_LIST
697 fprintf(fp, "%s\n", buf);
698 fflush(fp);
699 fclose(fp);
700 #endif
701 }
702 /* inter-view reference picture */
703 {
704 H264dVdpuPriv_t *priv = (H264dVdpuPriv_t *)p_hal->priv;
705 if (pp->curr_layer_id && priv->ilt_dpb && priv->ilt_dpb->valid) {
706 mpp_buf_slot_get_prop(p_hal->frame_slots,
707 priv->ilt_dpb->slot_index,
708 SLOT_BUFFER, &frame_buf);
709 p_regs->sw99.ref15_st_addr = mpp_buffer_get_fd(frame_buf); //!< inter-view base, ref15
710 p_regs->sw108.refpic_valid_flag |= (pp->field_pic_flag
711 ? 0x3 : 0x10000);
712 }
713 }
714 p_regs->sw50.dec_fixed_quant = pp->curr_layer_id; //!< VDPU_MVC_E
715 p_regs->sw50.dblk_flt_dis = 0; //!< filterDisable = 0;
716 mpp_buf_slot_get_prop(p_hal->frame_slots,
717 pp->CurrPic.Index7Bits,
718 SLOT_BUFFER, &frame_buf); //!< current out phy addr
719 outPhyAddr = mpp_buffer_get_fd(frame_buf);
720 if (pp->field_pic_flag && pp->CurrPic.AssociatedFlag) {
721 mpp_dev_set_reg_offset(p_hal->dev, 63, ((pp->wFrameWidthInMbsMinus1 + 1) * 16));
722 }
723 p_regs->sw63.dec_out_st_adr = outPhyAddr; //!< outPhyAddr, pp->CurrPic.Index7Bits
724 p_regs->sw110.flt_offset_cb_qp = pp->chroma_qp_index_offset;
725 p_regs->sw110.flt_offset_cr_qp = pp->second_chroma_qp_index_offset;
726 /* set default value for register[41] to avoid illegal translation fd */
727 {
728 RK_U32 dirMvOffset = 0;
729 RK_U32 picSizeInMbs = 0;
730
731 picSizeInMbs = p_hal->pp->wFrameWidthInMbsMinus1 + 1;
732 picSizeInMbs = picSizeInMbs
733 * (2 - pp->frame_mbs_only_flag) * (pp->wFrameHeightInMbsMinus1 + 1);
734 dirMvOffset = picSizeInMbs
735 * ((p_hal->pp->chroma_format_idc == 0) ? 256 : 384);
736 dirMvOffset += (pp->field_pic_flag && pp->CurrPic.AssociatedFlag)
737 ? (picSizeInMbs * 32) : 0;
738 if (dirMvOffset) {
739 RK_U32 offset = mpp_get_ioctl_version() ? dirMvOffset : dirMvOffset >> 4;
740 mpp_dev_set_reg_offset(p_hal->dev, 62, offset);
741 }
742 p_regs->sw62.dmmv_st_adr = mpp_buffer_get_fd(frame_buf);
743 }
744 p_regs->sw57.dmmv_wr_en = (p_long->nal_ref_idc != 0) ? 1 : 0; //!< defalut set 1
745 p_regs->sw115.dlmv_method_en = pp->direct_8x8_inference_flag;
746 p_regs->sw115.weight_pred_en = pp->weighted_pred_flag;
747 p_regs->sw111.wp_bslice_sel = pp->weighted_bipred_idc;
748 p_regs->sw114.max_refidx1 = (pp->num_ref_idx_l1_active_minus1 + 1);
749 p_regs->sw115.fieldpic_flag_exist = (!pp->frame_mbs_only_flag) ? 1 : 0;
750 p_regs->sw57.curpic_code_sel = (!pp->frame_mbs_only_flag
751 && (pp->MbaffFrameFlag || pp->field_pic_flag)) ? 1 : 0;
752 p_regs->sw57.curpic_stru_sel = pp->field_pic_flag;
753 p_regs->sw57.pic_decfield_sel = (!pp->CurrPic.AssociatedFlag) ? 1 : 0; //!< bottomFieldFlag
754 p_regs->sw57.sequ_mbaff_en = pp->MbaffFrameFlag;
755 p_regs->sw115.tranf_8x8_flag_en = pp->transform_8x8_mode_flag;
756 p_regs->sw115.monochr_en = (p_long->profileIdc >= 100
757 && pp->chroma_format_idc == 0) ? 1 : 0;
758 p_regs->sw115.scl_matrix_en = pp->scaleing_list_enable_flag;
759 {
760 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
761 if (p_hal->pp->scaleing_list_enable_flag) {
762 RK_U32 temp = 0;
763 RK_U32 *ptr = (RK_U32 *)reg_ctx->sclst_ptr;
764
765 for (i = 0; i < 6; i++) {
766 for (j = 0; j < 4; j++) {
767 temp = (p_hal->qm->bScalingLists4x4[i][4 * j + 0] << 24) |
768 (p_hal->qm->bScalingLists4x4[i][4 * j + 1] << 16) |
769 (p_hal->qm->bScalingLists4x4[i][4 * j + 2] << 8) |
770 (p_hal->qm->bScalingLists4x4[i][4 * j + 3]);
771 *ptr++ = temp;
772 }
773 }
774 for (i = 0; i < 2; i++) {
775 for (j = 0; j < 16; j++) {
776 temp = (p_hal->qm->bScalingLists8x8[i][4 * j + 0] << 24) |
777 (p_hal->qm->bScalingLists8x8[i][4 * j + 1] << 16) |
778 (p_hal->qm->bScalingLists8x8[i][4 * j + 2] << 8) |
779 (p_hal->qm->bScalingLists8x8[i][4 * j + 3]);
780 *ptr++ = temp;
781 }
782 }
783 }
784 p_regs->sw61.qtable_st_adr = mpp_buffer_get_fd(reg_ctx->buf);
785 }
786 p_regs->sw57.dec_wr_extmen_dis = 0; //!< set defalut 0
787 p_regs->sw57.addit_ch_fmt_wen = 0;
788 p_regs->sw57.dec_st_work = 1;
789
790 return ret = MPP_OK;
791 }
792
793 /*!
794 ***********************************************************************
795 * \brief
796 * init VDPU granite decoder
797 ***********************************************************************
798 */
799 //extern "C"
vdpu2_h264d_init(void * hal,MppHalCfg * cfg)800 MPP_RET vdpu2_h264d_init(void *hal, MppHalCfg *cfg)
801 {
802 MPP_RET ret = MPP_ERR_UNKNOW;
803 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
804 INP_CHECK(ret, NULL == hal);
805 (void) cfg;
806
807 MEM_CHECK(ret, p_hal->priv = mpp_calloc_size(void,
808 sizeof(H264dVdpuPriv_t)));
809 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(H264dVdpuRegCtx_t)));
810 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
811 //!< malloc buffers
812 {
813 RK_U32 i = 0;
814 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
815
816 RK_U32 buf_size = VDPU_CABAC_TAB_SIZE + VDPU_POC_BUF_SIZE + VDPU_SCALING_LIST_SIZE;
817 for (i = 0; i < loop; i++) {
818 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, ®_ctx->reg_buf[i].buf, buf_size));
819 reg_ctx->reg_buf[i].cabac_ptr = mpp_buffer_get_ptr(reg_ctx->reg_buf[i].buf);
820 reg_ctx->reg_buf[i].poc_ptr = reg_ctx->reg_buf[i].cabac_ptr + VDPU_CABAC_TAB_SIZE;
821 reg_ctx->reg_buf[i].sclst_ptr = reg_ctx->reg_buf[i].poc_ptr + VDPU_POC_BUF_SIZE;
822 reg_ctx->reg_buf[i].regs = mpp_calloc_size(void, sizeof(H264dVdpuRegs_t));
823 //!< copy cabac table bytes
824 memcpy(reg_ctx->reg_buf[i].cabac_ptr, (void *)vdpu_cabac_table, sizeof(vdpu_cabac_table));
825 }
826 }
827
828 if (!p_hal->fast_mode) {
829 reg_ctx->buf = reg_ctx->reg_buf[0].buf;
830 reg_ctx->cabac_ptr = reg_ctx->reg_buf[0].cabac_ptr;
831 reg_ctx->poc_ptr = reg_ctx->reg_buf[0].poc_ptr;
832 reg_ctx->sclst_ptr = reg_ctx->reg_buf[0].sclst_ptr;
833 reg_ctx->regs = reg_ctx->reg_buf[0].regs;
834 }
835
836 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, vdpu_hor_align);
837 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, vdpu_ver_align);
838
839 __RETURN:
840 return MPP_OK;
841 __FAILED:
842 vdpu2_h264d_deinit(hal);
843
844 return ret;
845 }
846
847
848 /*!
849 ***********************************************************************
850 * \brief
851 * deinit
852 ***********************************************************************
853 */
854 //extern "C"
vdpu2_h264d_deinit(void * hal)855 MPP_RET vdpu2_h264d_deinit(void *hal)
856 {
857 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
858 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
859
860 RK_U32 i = 0;
861 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
862 for (i = 0; i < loop; i++) {
863 MPP_FREE(reg_ctx->reg_buf[i].regs);
864 mpp_buffer_put(reg_ctx->reg_buf[i].buf);
865 }
866
867 MPP_FREE(p_hal->reg_ctx);
868 MPP_FREE(p_hal->priv);
869
870 return MPP_OK;
871 }
872 /*!
873 ***********************************************************************
874 * \brief
875 * generate register
876 ***********************************************************************
877 */
878 //extern "C"
vdpu2_h264d_gen_regs(void * hal,HalTaskInfo * task)879 MPP_RET vdpu2_h264d_gen_regs(void *hal, HalTaskInfo *task)
880 {
881 MPP_RET ret = MPP_ERR_UNKNOW;
882
883 H264dVdpuPriv_t *priv = NULL;
884 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
885 INP_CHECK(ret, NULL == p_hal);
886 p_hal->in_task = &task->dec;
887
888 if (task->dec.flags.parse_err ||
889 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {
890 goto __RETURN;
891 }
892 priv = p_hal->priv;
893 priv->layed_id = p_hal->pp->curr_layer_id;
894
895 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
896 if (p_hal->fast_mode) {
897 RK_U32 i = 0;
898 for (i = 0; i < MPP_ARRAY_ELEMS(reg_ctx->reg_buf); i++) {
899 if (!reg_ctx->reg_buf[i].valid) {
900 task->dec.reg_index = i;
901 reg_ctx->buf = reg_ctx->reg_buf[i].buf;
902 reg_ctx->cabac_ptr = reg_ctx->reg_buf[i].cabac_ptr;
903 reg_ctx->poc_ptr = reg_ctx->reg_buf[i].poc_ptr;
904 reg_ctx->sclst_ptr = reg_ctx->reg_buf[i].sclst_ptr;
905 reg_ctx->regs = reg_ctx->reg_buf[i].regs;
906 reg_ctx->reg_buf[i].valid = 1;
907 break;
908 }
909 }
910 }
911
912 FUN_CHECK(ret = adjust_input(priv, &p_hal->slice_long[0], p_hal->pp));
913 FUN_CHECK(ret = set_device_regs(p_hal, (H264dVdpuRegs_t *)reg_ctx->regs));
914 FUN_CHECK(ret = set_pic_regs(p_hal, (H264dVdpuRegs_t *)reg_ctx->regs));
915 FUN_CHECK(ret = set_vlc_regs(p_hal, (H264dVdpuRegs_t *)reg_ctx->regs));
916 FUN_CHECK(ret = set_ref_regs(p_hal, (H264dVdpuRegs_t *)reg_ctx->regs));
917 FUN_CHECK(ret = set_asic_regs(p_hal, (H264dVdpuRegs_t *)reg_ctx->regs));
918 mpp_buffer_sync_end(reg_ctx->buf);
919
920 __RETURN:
921 return ret = MPP_OK;
922 __FAILED:
923 return ret;
924 }
925 /*!
926 ***********************************************************************
927 * \brief h
928 * start hard
929 ***********************************************************************
930 */
931 //extern "C"
vdpu2_h264d_start(void * hal,HalTaskInfo * task)932 MPP_RET vdpu2_h264d_start(void *hal, HalTaskInfo *task)
933 {
934 MPP_RET ret = MPP_ERR_UNKNOW;
935 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
936 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
937 H264dVdpuRegs_t *p_regs = p_hal->fast_mode ?
938 (H264dVdpuRegs_t *)reg_ctx->reg_buf[task->dec.reg_index].regs :
939 (H264dVdpuRegs_t *)reg_ctx->regs;
940 RK_U32 w = p_regs->sw110.pic_mb_w * 16;
941 RK_U32 h = p_regs->sw110.pic_mb_h * 16;
942 RK_U32 cache_en = 1;
943 RockchipSocType soc_type = mpp_get_soc_type();
944
945 if (task->dec.flags.parse_err ||
946 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {
947 goto __RETURN;
948 }
949
950 if (soc_type == ROCKCHIP_SOC_RK3326 ||
951 soc_type == ROCKCHIP_SOC_PX30 ||
952 soc_type == ROCKCHIP_SOC_RK3228H)
953 cache_en = ((w * h) >= (1280 * 720)) ? 1 : 0;
954
955 p_regs->sw57.cache_en = cache_en;
956 p_regs->sw57.pref_sigchan = 1;
957 p_regs->sw56.bus_pos_sel = 1;
958 p_regs->sw57.intra_dbl3t = 1;
959 p_regs->sw57.inter_dblspeed = 1;
960 p_regs->sw57.intra_dblspeed = 1;
961
962 #if DEBUG_REF_LIST
963 {
964 char file_name[128];
965 sprintf(file_name, "/sdcard/test/mpp2_reg_dump_log.txt");
966 FILE *fp = fopen(file_name, "ab");
967 char buf[2048];
968 RK_S32 buf_len = 0, buf_size = sizeof(buf) - 1;
969 RK_U32 *reg_tmp = (RK_U32*)reg_ctx->regs;
970 RK_U32 i;
971
972 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "=== reg dump fram_num %d ===\n",
973 p_hal->pp->frame_num);
974 for (i = 50; i < 116; i++) {
975 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "Regs[%d] = 0x%08x\n", i, reg_tmp[i]);
976 }
977 fprintf(fp, "%s", buf);
978
979 fflush(fp);
980 fclose(fp);
981 }
982 #endif
983 do {
984 MppDevRegWrCfg wr_cfg;
985 MppDevRegRdCfg rd_cfg;
986 RK_U32 reg_size = DEC_VDPU_REGISTERS * sizeof(RK_U32);
987
988 wr_cfg.reg = reg_ctx->regs;
989 wr_cfg.size = reg_size;
990 wr_cfg.offset = 0;
991
992 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_WR, &wr_cfg);
993 if (ret) {
994 mpp_err_f("set register write failed %d\n", ret);
995 break;
996 }
997
998 rd_cfg.reg = reg_ctx->regs;
999 rd_cfg.size = reg_size;
1000 rd_cfg.offset = 0;
1001
1002 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_RD, &rd_cfg);
1003 if (ret) {
1004 mpp_err_f("set register read failed %d\n", ret);
1005 break;
1006 }
1007
1008 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_SEND, NULL);
1009 if (ret) {
1010 mpp_err_f("send cmd failed %d\n", ret);
1011 break;
1012 }
1013 } while (0);
1014
1015 __RETURN:
1016 (void)task;
1017 return ret = MPP_OK;
1018 }
1019 /*!
1020 ***********************************************************************
1021 * \brief
1022 * wait hard
1023 ***********************************************************************
1024 */
1025 //extern "C"
vdpu2_h264d_wait(void * hal,HalTaskInfo * task)1026 MPP_RET vdpu2_h264d_wait(void *hal, HalTaskInfo *task)
1027 {
1028 MPP_RET ret = MPP_ERR_UNKNOW;
1029 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1030 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
1031 H264dVdpuRegs_t *p_regs = (H264dVdpuRegs_t *)(p_hal->fast_mode ?
1032 reg_ctx->reg_buf[task->dec.reg_index].regs :
1033 reg_ctx->regs);
1034
1035 if (task->dec.flags.parse_err ||
1036 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {
1037 goto __SKIP_HARD;
1038 }
1039
1040 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL);
1041 if (ret)
1042 mpp_err_f("poll cmd failed %d\n", ret);
1043
1044 __SKIP_HARD:
1045 if (p_hal->dec_cb) {
1046 DecCbHalDone param;
1047
1048 param.task = (void *)&task->dec;
1049 param.regs = (RK_U32 *)reg_ctx->regs;
1050 param.hard_err = !p_regs->sw55.dec_rdy_sts;
1051
1052 mpp_callback(p_hal->dec_cb, ¶m);
1053 }
1054 memset(&p_regs->sw55, 0, sizeof(RK_U32));
1055 if (p_hal->fast_mode) {
1056 reg_ctx->reg_buf[task->dec.reg_index].valid = 0;
1057 }
1058
1059 (void)task;
1060
1061 return ret = MPP_OK;
1062 }
1063 /*!
1064 ***********************************************************************
1065 * \brief
1066 * reset
1067 ***********************************************************************
1068 */
1069 //extern "C"
vdpu2_h264d_reset(void * hal)1070 MPP_RET vdpu2_h264d_reset(void *hal)
1071 {
1072 MPP_RET ret = MPP_ERR_UNKNOW;
1073 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1074
1075 INP_CHECK(ret, NULL == p_hal);
1076
1077 memset(p_hal->priv, 0, sizeof(H264dVdpuPriv_t));
1078
1079 __RETURN:
1080 return ret = MPP_OK;
1081 }
1082 /*!
1083 ***********************************************************************
1084 * \brief
1085 * flush
1086 ***********************************************************************
1087 */
1088 //extern "C"
vdpu2_h264d_flush(void * hal)1089 MPP_RET vdpu2_h264d_flush(void *hal)
1090 {
1091 MPP_RET ret = MPP_ERR_UNKNOW;
1092 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1093
1094 INP_CHECK(ret, NULL == p_hal);
1095
1096 __RETURN:
1097 return ret = MPP_OK;
1098 }
1099 /*!
1100 ***********************************************************************
1101 * \brief
1102 * control
1103 ***********************************************************************
1104 */
1105 //extern "C"
vdpu2_h264d_control(void * hal,MpiCmd cmd_type,void * param)1106 MPP_RET vdpu2_h264d_control(void *hal, MpiCmd cmd_type, void *param)
1107 {
1108 MPP_RET ret = MPP_ERR_UNKNOW;
1109 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1110
1111 INP_CHECK(ret, NULL == p_hal);
1112
1113 (void)hal;
1114 (void)cmd_type;
1115 (void)param;
1116 __RETURN:
1117 return ret = MPP_OK;
1118 }
1119
1120 const MppHalApi hal_h264d_vdpu2 = {
1121 .name = "h264d_vdpu2",
1122 .type = MPP_CTX_DEC,
1123 .coding = MPP_VIDEO_CodingAVC,
1124 .ctx_size = sizeof(H264dVdpuRegCtx_t),
1125 .flag = 0,
1126 .init = vdpu2_h264d_init,
1127 .deinit = vdpu2_h264d_deinit,
1128 .reg_gen = vdpu2_h264d_gen_regs,
1129 .start = vdpu2_h264d_start,
1130 .wait = vdpu2_h264d_wait,
1131 .reset = vdpu2_h264d_reset,
1132 .flush = vdpu2_h264d_flush,
1133 .control = vdpu2_h264d_control,
1134 };
1135