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Searched refs:SCLK_OTGPHY0 (Results 1 – 25 of 32) sorted by relevance

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/OK3568_Linux_fs/u-boot/include/dt-bindings/clock/
H A Drk3036-cru.h33 #define SCLK_OTGPHY0 93 macro
H A Drk3188-cru-common.h38 #define SCLK_OTGPHY0 81 macro
H A Drk3128-cru.h56 #define SCLK_OTGPHY0 142 macro
H A Drk3228-cru.h65 #define SCLK_OTGPHY0 142 macro
H A Drk3368-cru.h53 #define SCLK_OTGPHY0 93 macro
H A Drk3288-cru.h46 #define SCLK_OTGPHY0 93 macro
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Drk3036-cru.h32 #define SCLK_OTGPHY0 93 macro
H A Drk3188-cru-common.h37 #define SCLK_OTGPHY0 81 macro
H A Drk3128-cru.h56 #define SCLK_OTGPHY0 142 macro
H A Drk3228-cru.h65 #define SCLK_OTGPHY0 142 macro
H A Drk3288-cru.h48 #define SCLK_OTGPHY0 93 macro
H A Drk3368-cru.h44 #define SCLK_OTGPHY0 93 macro
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-rk3036.c335 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", CLK_IGNORE_UNUSED,
H A Dclk-rk3128.c386 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", 0,
H A Dclk-rk3228.c462 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 0,
H A Dclk-rk3188.c350 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
H A Dclk-rk3368.c584 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
H A Dclk-rk3288.c571 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3036.dtsi232 clocks = <&cru SCLK_OTGPHY0>;
H A Drk3188.dtsi152 clocks = <&cru SCLK_OTGPHY0>;
H A Drk3066a.dtsi197 clocks = <&cru SCLK_OTGPHY0>;
H A Drk3288-veyron.dtsi830 assigned-clock-parents = <&cru SCLK_OTGPHY0>;
H A Drk3128.dtsi654 clocks = <&cru SCLK_OTGPHY0>;
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Drk3188.dtsi234 clocks = <&cru SCLK_OTGPHY0>;
H A Drk3066a.dtsi397 clocks = <&cru SCLK_OTGPHY0>;

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