1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2013 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/clock/rk3188-cru.h> 10#include <dt-bindings/power/rk3188-power.h> 11#include "rk3xxx.dtsi" 12 13/ { 14 compatible = "rockchip,rk3188"; 15 16 aliases { 17 gpio0 = &gpio0; 18 gpio1 = &gpio1; 19 gpio2 = &gpio2; 20 gpio3 = &gpio3; 21 }; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 enable-method = "rockchip,rk3066-smp"; 27 28 cpu0: cpu@0 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a9"; 31 next-level-cache = <&L2>; 32 reg = <0x0>; 33 clock-latency = <40000>; 34 clocks = <&cru ARMCLK>; 35 operating-points-v2 = <&cpu0_opp_table>; 36 resets = <&cru SRST_CORE0>; 37 }; 38 cpu1: cpu@1 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a9"; 41 next-level-cache = <&L2>; 42 reg = <0x1>; 43 operating-points-v2 = <&cpu0_opp_table>; 44 resets = <&cru SRST_CORE1>; 45 }; 46 cpu2: cpu@2 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a9"; 49 next-level-cache = <&L2>; 50 reg = <0x2>; 51 operating-points-v2 = <&cpu0_opp_table>; 52 resets = <&cru SRST_CORE2>; 53 }; 54 cpu3: cpu@3 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a9"; 57 next-level-cache = <&L2>; 58 reg = <0x3>; 59 operating-points-v2 = <&cpu0_opp_table>; 60 resets = <&cru SRST_CORE3>; 61 }; 62 }; 63 64 cpu0_opp_table: opp_table0 { 65 compatible = "operating-points-v2"; 66 opp-shared; 67 68 opp-312000000 { 69 opp-hz = /bits/ 64 <312000000>; 70 opp-microvolt = <875000>; 71 clock-latency-ns = <40000>; 72 }; 73 opp-504000000 { 74 opp-hz = /bits/ 64 <504000000>; 75 opp-microvolt = <925000>; 76 }; 77 opp-600000000 { 78 opp-hz = /bits/ 64 <600000000>; 79 opp-microvolt = <950000>; 80 opp-suspend; 81 }; 82 opp-816000000 { 83 opp-hz = /bits/ 64 <816000000>; 84 opp-microvolt = <975000>; 85 }; 86 opp-1008000000 { 87 opp-hz = /bits/ 64 <1008000000>; 88 opp-microvolt = <1075000>; 89 }; 90 opp-1200000000 { 91 opp-hz = /bits/ 64 <1200000000>; 92 opp-microvolt = <1150000>; 93 }; 94 opp-1416000000 { 95 opp-hz = /bits/ 64 <1416000000>; 96 opp-microvolt = <1250000>; 97 }; 98 opp-1608000000 { 99 opp-hz = /bits/ 64 <1608000000>; 100 opp-microvolt = <1350000>; 101 }; 102 }; 103 104 display-subsystem { 105 compatible = "rockchip,display-subsystem"; 106 ports = <&vop0_out>, <&vop1_out>; 107 }; 108 109 sram: sram@10080000 { 110 compatible = "mmio-sram"; 111 reg = <0x10080000 0x8000>; 112 #address-cells = <1>; 113 #size-cells = <1>; 114 ranges = <0 0x10080000 0x8000>; 115 116 smp-sram@0 { 117 compatible = "rockchip,rk3066-smp-sram"; 118 reg = <0x0 0x50>; 119 }; 120 }; 121 122 vop0: vop@1010c000 { 123 compatible = "rockchip,rk3188-vop"; 124 reg = <0x1010c000 0x1000>; 125 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 126 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>; 127 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 128 power-domains = <&power RK3188_PD_VIO>; 129 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 130 reset-names = "axi", "ahb", "dclk"; 131 status = "disabled"; 132 133 vop0_out: port { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 }; 137 }; 138 139 vop1: vop@1010e000 { 140 compatible = "rockchip,rk3188-vop"; 141 reg = <0x1010e000 0x1000>; 142 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 143 clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>; 144 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 145 power-domains = <&power RK3188_PD_VIO>; 146 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 147 reset-names = "axi", "ahb", "dclk"; 148 status = "disabled"; 149 150 vop1_out: port { 151 #address-cells = <1>; 152 #size-cells = <0>; 153 }; 154 }; 155 156 timer3: timer@2000e000 { 157 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; 158 reg = <0x2000e000 0x20>; 159 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>; 161 clock-names = "pclk", "timer"; 162 }; 163 164 timer6: timer@200380a0 { 165 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; 166 reg = <0x200380a0 0x20>; 167 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 168 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>; 169 clock-names = "pclk", "timer"; 170 }; 171 172 i2s0: i2s@1011a000 { 173 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; 174 reg = <0x1011a000 0x2000>; 175 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 176 pinctrl-names = "default"; 177 pinctrl-0 = <&i2s0_bus>; 178 dmas = <&dmac1_s 6>, <&dmac1_s 7>; 179 dma-names = "tx", "rx"; 180 clock-names = "i2s_hclk", "i2s_clk"; 181 clocks = <&cru HCLK_I2S0_2CH>, <&cru SCLK_I2S0>; 182 rockchip,playback-channels = <2>; 183 rockchip,capture-channels = <2>; 184 #sound-dai-cells = <0>; 185 status = "disabled"; 186 }; 187 188 spdif: sound@1011e000 { 189 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; 190 reg = <0x1011e000 0x2000>; 191 #sound-dai-cells = <0>; 192 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; 193 clock-names = "mclk", "hclk"; 194 dmas = <&dmac1_s 8>; 195 dma-names = "tx"; 196 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 197 pinctrl-names = "default"; 198 pinctrl-0 = <&spdif_tx>; 199 status = "disabled"; 200 }; 201 202 cru: clock-controller@20000000 { 203 compatible = "rockchip,rk3188-cru"; 204 reg = <0x20000000 0x1000>; 205 rockchip,grf = <&grf>; 206 207 #clock-cells = <1>; 208 #reset-cells = <1>; 209 }; 210 211 efuse: efuse@20010000 { 212 compatible = "rockchip,rk3188-efuse"; 213 reg = <0x20010000 0x4000>; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 clocks = <&cru PCLK_EFUSE>; 217 clock-names = "pclk_efuse"; 218 219 cpu_leakage: cpu_leakage@17 { 220 reg = <0x17 0x1>; 221 }; 222 }; 223 224 usbphy: phy { 225 compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy"; 226 rockchip,grf = <&grf>; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 status = "disabled"; 230 231 usbphy0: usb-phy@10c { 232 #phy-cells = <0>; 233 reg = <0x10c>; 234 clocks = <&cru SCLK_OTGPHY0>; 235 clock-names = "phyclk"; 236 #clock-cells = <0>; 237 }; 238 239 usbphy1: usb-phy@11c { 240 #phy-cells = <0>; 241 reg = <0x11c>; 242 clocks = <&cru SCLK_OTGPHY1>; 243 clock-names = "phyclk"; 244 #clock-cells = <0>; 245 }; 246 }; 247 248 pinctrl: pinctrl { 249 compatible = "rockchip,rk3188-pinctrl"; 250 rockchip,grf = <&grf>; 251 rockchip,pmu = <&pmu>; 252 253 #address-cells = <1>; 254 #size-cells = <1>; 255 ranges; 256 257 gpio0: gpio0@2000a000 { 258 compatible = "rockchip,rk3188-gpio-bank0"; 259 reg = <0x2000a000 0x100>; 260 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 261 clock-names = "bus"; 262 clocks = <&cru PCLK_GPIO0>; 263 264 gpio-controller; 265 #gpio-cells = <2>; 266 267 interrupt-controller; 268 #interrupt-cells = <2>; 269 }; 270 271 gpio1: gpio1@2003c000 { 272 compatible = "rockchip,gpio-bank"; 273 reg = <0x2003c000 0x100>; 274 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 275 clock-names = "bus"; 276 clocks = <&cru PCLK_GPIO1>; 277 278 gpio-controller; 279 #gpio-cells = <2>; 280 281 interrupt-controller; 282 #interrupt-cells = <2>; 283 }; 284 285 gpio2: gpio2@2003e000 { 286 compatible = "rockchip,gpio-bank"; 287 reg = <0x2003e000 0x100>; 288 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 289 clock-names = "bus"; 290 clocks = <&cru PCLK_GPIO2>; 291 292 gpio-controller; 293 #gpio-cells = <2>; 294 295 interrupt-controller; 296 #interrupt-cells = <2>; 297 }; 298 299 gpio3: gpio3@20080000 { 300 compatible = "rockchip,gpio-bank"; 301 reg = <0x20080000 0x100>; 302 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 303 clock-names = "bus"; 304 clocks = <&cru PCLK_GPIO3>; 305 306 gpio-controller; 307 #gpio-cells = <2>; 308 309 interrupt-controller; 310 #interrupt-cells = <2>; 311 }; 312 313 pcfg_pull_up: pcfg_pull_up { 314 bias-pull-up; 315 }; 316 317 pcfg_pull_down: pcfg_pull_down { 318 bias-pull-down; 319 }; 320 321 pcfg_pull_none: pcfg_pull_none { 322 bias-disable; 323 }; 324 325 emmc { 326 emmc_clk: emmc-clk { 327 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; 328 }; 329 330 emmc_cmd: emmc-cmd { 331 rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>; 332 }; 333 334 emmc_rst: emmc-rst { 335 rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>; 336 }; 337 338 /* 339 * The data pins are shared between nandc and emmc and 340 * not accessible through pinctrl. Also they should've 341 * been already set correctly by firmware, as 342 * flash/emmc is the boot-device. 343 */ 344 }; 345 346 emac { 347 emac_xfer: emac-xfer { 348 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */ 349 <3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */ 350 <3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */ 351 <3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */ 352 <3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */ 353 <3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */ 354 <3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */ 355 <3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */ 356 }; 357 358 emac_mdio: emac-mdio { 359 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, 360 <3 RK_PD1 2 &pcfg_pull_none>; 361 }; 362 }; 363 364 i2c0 { 365 i2c0_xfer: i2c0-xfer { 366 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 367 <1 RK_PD1 1 &pcfg_pull_none>; 368 }; 369 }; 370 371 i2c1 { 372 i2c1_xfer: i2c1-xfer { 373 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>, 374 <1 RK_PD3 1 &pcfg_pull_none>; 375 }; 376 }; 377 378 i2c2 { 379 i2c2_xfer: i2c2-xfer { 380 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>, 381 <1 RK_PD5 1 &pcfg_pull_none>; 382 }; 383 }; 384 385 i2c3 { 386 i2c3_xfer: i2c3-xfer { 387 rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>, 388 <3 RK_PB7 2 &pcfg_pull_none>; 389 }; 390 }; 391 392 i2c4 { 393 i2c4_xfer: i2c4-xfer { 394 rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>, 395 <1 RK_PD7 1 &pcfg_pull_none>; 396 }; 397 }; 398 399 lcdc1 { 400 lcdc1_dclk: lcdc1-dclk { 401 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>; 402 }; 403 404 lcdc1_den: lcdc1-den { 405 rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>; 406 }; 407 408 lcdc1_hsync: lcdc1-hsync { 409 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; 410 }; 411 412 lcdc1_vsync: lcdc1-vsync { 413 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; 414 }; 415 416 lcdc1_rgb24: lcdc1-rgb24 { 417 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, 418 <2 RK_PA1 1 &pcfg_pull_none>, 419 <2 RK_PA2 1 &pcfg_pull_none>, 420 <2 RK_PA3 1 &pcfg_pull_none>, 421 <2 RK_PA4 1 &pcfg_pull_none>, 422 <2 RK_PA5 1 &pcfg_pull_none>, 423 <2 RK_PA6 1 &pcfg_pull_none>, 424 <2 RK_PA7 1 &pcfg_pull_none>, 425 <2 RK_PB0 1 &pcfg_pull_none>, 426 <2 RK_PB1 1 &pcfg_pull_none>, 427 <2 RK_PB2 1 &pcfg_pull_none>, 428 <2 RK_PB3 1 &pcfg_pull_none>, 429 <2 RK_PB4 1 &pcfg_pull_none>, 430 <2 RK_PB5 1 &pcfg_pull_none>, 431 <2 RK_PB6 1 &pcfg_pull_none>, 432 <2 RK_PB7 1 &pcfg_pull_none>, 433 <2 RK_PC0 1 &pcfg_pull_none>, 434 <2 RK_PC1 1 &pcfg_pull_none>, 435 <2 RK_PC2 1 &pcfg_pull_none>, 436 <2 RK_PC3 1 &pcfg_pull_none>, 437 <2 RK_PC4 1 &pcfg_pull_none>, 438 <2 RK_PC5 1 &pcfg_pull_none>, 439 <2 RK_PC6 1 &pcfg_pull_none>, 440 <2 RK_PC7 1 &pcfg_pull_none>; 441 }; 442 }; 443 444 pwm0 { 445 pwm0_out: pwm0-out { 446 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 447 }; 448 }; 449 450 pwm1 { 451 pwm1_out: pwm1-out { 452 rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>; 453 }; 454 }; 455 456 pwm2 { 457 pwm2_out: pwm2-out { 458 rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>; 459 }; 460 }; 461 462 pwm3 { 463 pwm3_out: pwm3-out { 464 rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>; 465 }; 466 }; 467 468 spi0 { 469 spi0_clk: spi0-clk { 470 rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>; 471 }; 472 spi0_cs0: spi0-cs0 { 473 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>; 474 }; 475 spi0_tx: spi0-tx { 476 rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>; 477 }; 478 spi0_rx: spi0-rx { 479 rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>; 480 }; 481 spi0_cs1: spi0-cs1 { 482 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>; 483 }; 484 }; 485 486 spi1 { 487 spi1_clk: spi1-clk { 488 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>; 489 }; 490 spi1_cs0: spi1-cs0 { 491 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>; 492 }; 493 spi1_rx: spi1-rx { 494 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>; 495 }; 496 spi1_tx: spi1-tx { 497 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>; 498 }; 499 spi1_cs1: spi1-cs1 { 500 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; 501 }; 502 }; 503 504 uart0 { 505 uart0_xfer: uart0-xfer { 506 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>, 507 <1 RK_PA1 1 &pcfg_pull_up>; 508 }; 509 510 uart0_cts: uart0-cts { 511 rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>; 512 }; 513 514 uart0_rts: uart0-rts { 515 rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>; 516 }; 517 }; 518 519 uart1 { 520 uart1_xfer: uart1-xfer { 521 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>, 522 <1 RK_PA5 1 &pcfg_pull_up>; 523 }; 524 525 uart1_cts: uart1-cts { 526 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 527 }; 528 529 uart1_rts: uart1-rts { 530 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>; 531 }; 532 }; 533 534 uart2 { 535 uart2_xfer: uart2-xfer { 536 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>, 537 <1 RK_PB1 1 &pcfg_pull_up>; 538 }; 539 /* no rts / cts for uart2 */ 540 }; 541 542 uart3 { 543 uart3_xfer: uart3-xfer { 544 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>, 545 <1 RK_PB3 1 &pcfg_pull_up>; 546 }; 547 548 uart3_cts: uart3-cts { 549 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>; 550 }; 551 552 uart3_rts: uart3-rts { 553 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>; 554 }; 555 }; 556 557 sd0 { 558 sd0_clk: sd0-clk { 559 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>; 560 }; 561 562 sd0_cmd: sd0-cmd { 563 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; 564 }; 565 566 sd0_cd: sd0-cd { 567 rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>; 568 }; 569 570 sd0_wp: sd0-wp { 571 rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>; 572 }; 573 574 sd0_pwr: sd0-pwr { 575 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; 576 }; 577 578 sd0_bus1: sd0-bus-width1 { 579 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; 580 }; 581 582 sd0_bus4: sd0-bus-width4 { 583 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, 584 <3 RK_PA5 1 &pcfg_pull_none>, 585 <3 RK_PA6 1 &pcfg_pull_none>, 586 <3 RK_PA7 1 &pcfg_pull_none>; 587 }; 588 }; 589 590 sd1 { 591 sd1_clk: sd1-clk { 592 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; 593 }; 594 595 sd1_cmd: sd1-cmd { 596 rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>; 597 }; 598 599 sd1_cd: sd1-cd { 600 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>; 601 }; 602 603 sd1_wp: sd1-wp { 604 rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>; 605 }; 606 607 sd1_bus1: sd1-bus-width1 { 608 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>; 609 }; 610 611 sd1_bus4: sd1-bus-width4 { 612 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>, 613 <3 RK_PC2 1 &pcfg_pull_none>, 614 <3 RK_PC3 1 &pcfg_pull_none>, 615 <3 RK_PC4 1 &pcfg_pull_none>; 616 }; 617 }; 618 619 i2s0 { 620 i2s0_bus: i2s0-bus { 621 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, 622 <1 RK_PC1 1 &pcfg_pull_none>, 623 <1 RK_PC2 1 &pcfg_pull_none>, 624 <1 RK_PC3 1 &pcfg_pull_none>, 625 <1 RK_PC4 1 &pcfg_pull_none>, 626 <1 RK_PC5 1 &pcfg_pull_none>; 627 }; 628 }; 629 630 spdif { 631 spdif_tx: spdif-tx { 632 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>; 633 }; 634 }; 635 }; 636}; 637 638&emac { 639 compatible = "rockchip,rk3188-emac"; 640}; 641 642&global_timer { 643 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 644}; 645 646&local_timer { 647 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 648}; 649 650&gpu { 651 compatible = "rockchip,rk3188-mali", "arm,mali-400"; 652 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 662 interrupt-names = "gp", 663 "gpmmu", 664 "pp0", 665 "ppmmu0", 666 "pp1", 667 "ppmmu1", 668 "pp2", 669 "ppmmu2", 670 "pp3", 671 "ppmmu3"; 672 power-domains = <&power RK3188_PD_GPU>; 673}; 674 675&i2c0 { 676 compatible = "rockchip,rk3188-i2c"; 677 pinctrl-names = "default"; 678 pinctrl-0 = <&i2c0_xfer>; 679}; 680 681&i2c1 { 682 compatible = "rockchip,rk3188-i2c"; 683 pinctrl-names = "default"; 684 pinctrl-0 = <&i2c1_xfer>; 685}; 686 687&i2c2 { 688 compatible = "rockchip,rk3188-i2c"; 689 pinctrl-names = "default"; 690 pinctrl-0 = <&i2c2_xfer>; 691}; 692 693&i2c3 { 694 compatible = "rockchip,rk3188-i2c"; 695 pinctrl-names = "default"; 696 pinctrl-0 = <&i2c3_xfer>; 697}; 698 699&i2c4 { 700 compatible = "rockchip,rk3188-i2c"; 701 pinctrl-names = "default"; 702 pinctrl-0 = <&i2c4_xfer>; 703}; 704 705&pmu { 706 power: power-controller { 707 compatible = "rockchip,rk3188-power-controller"; 708 #power-domain-cells = <1>; 709 #address-cells = <1>; 710 #size-cells = <0>; 711 712 power-domain@RK3188_PD_VIO { 713 reg = <RK3188_PD_VIO>; 714 clocks = <&cru ACLK_LCDC0>, 715 <&cru ACLK_LCDC1>, 716 <&cru DCLK_LCDC0>, 717 <&cru DCLK_LCDC1>, 718 <&cru HCLK_LCDC0>, 719 <&cru HCLK_LCDC1>, 720 <&cru SCLK_CIF0>, 721 <&cru ACLK_CIF0>, 722 <&cru HCLK_CIF0>, 723 <&cru ACLK_IPP>, 724 <&cru HCLK_IPP>, 725 <&cru ACLK_RGA>, 726 <&cru HCLK_RGA>; 727 pm_qos = <&qos_lcdc0>, 728 <&qos_lcdc1>, 729 <&qos_cif0>, 730 <&qos_ipp>, 731 <&qos_rga>; 732 }; 733 734 power-domain@RK3188_PD_VIDEO { 735 reg = <RK3188_PD_VIDEO>; 736 clocks = <&cru ACLK_VDPU>, 737 <&cru ACLK_VEPU>, 738 <&cru HCLK_VDPU>, 739 <&cru HCLK_VEPU>; 740 pm_qos = <&qos_vpu>; 741 }; 742 743 power-domain@RK3188_PD_GPU { 744 reg = <RK3188_PD_GPU>; 745 clocks = <&cru ACLK_GPU>; 746 pm_qos = <&qos_gpu>; 747 }; 748 }; 749}; 750 751&pwm0 { 752 pinctrl-names = "active"; 753 pinctrl-0 = <&pwm0_out>; 754}; 755 756&pwm1 { 757 pinctrl-names = "active"; 758 pinctrl-0 = <&pwm1_out>; 759}; 760 761&pwm2 { 762 pinctrl-names = "active"; 763 pinctrl-0 = <&pwm2_out>; 764}; 765 766&pwm3 { 767 pinctrl-names = "active"; 768 pinctrl-0 = <&pwm3_out>; 769}; 770 771&spi0 { 772 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; 773 pinctrl-names = "default"; 774 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 775}; 776 777&spi1 { 778 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; 779 pinctrl-names = "default"; 780 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 781}; 782 783&uart0 { 784 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; 785 pinctrl-names = "default"; 786 pinctrl-0 = <&uart0_xfer>; 787}; 788 789&uart1 { 790 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; 791 pinctrl-names = "default"; 792 pinctrl-0 = <&uart1_xfer>; 793}; 794 795&uart2 { 796 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; 797 pinctrl-names = "default"; 798 pinctrl-0 = <&uart2_xfer>; 799}; 800 801&uart3 { 802 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&uart3_xfer>; 805}; 806 807&wdt { 808 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; 809}; 810