1/* 2 * SPDX-License-Identifier: GPL-2.0+ 3 */ 4 5#include <dt-bindings/gpio/gpio.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/clock/rk3036-cru.h> 10#include "skeleton.dtsi" 11 12/ { 13 compatible = "rockchip,rk3036"; 14 15 interrupt-parent = <&gic>; 16 17 aliases { 18 gpio0 = &gpio0; 19 gpio1 = &gpio1; 20 gpio2 = &gpio2; 21 i2c1 = &i2c1; 22 serial0 = &uart0; 23 serial1 = &uart1; 24 serial2 = &uart2; 25 mmc0 = &emmc; 26 mmc1 = &sdmmc; 27 }; 28 29 memory { 30 device_type = "memory"; 31 reg = <0x60000000 0x40000000>; 32 }; 33 34 arm-pmu { 35 compatible = "arm,cortex-a7-pmu"; 36 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 38 interrupt-affinity = <&cpu0>, <&cpu1>; 39 }; 40 41 cpus { 42 #address-cells = <1>; 43 #size-cells = <0>; 44 enable-method = "rockchip,rk3036-smp"; 45 46 cpu0: cpu@f00 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 reg = <0xf00>; 50 operating-points = < 51 /* KHz uV */ 52 816000 1000000 53 >; 54 #cooling-cells = <2>; /* min followed by max */ 55 clock-latency = <40000>; 56 clocks = <&cru ARMCLK>; 57 resets = <&cru SRST_CORE0>; 58 }; 59 cpu1: cpu@f01 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a7"; 62 reg = <0xf01>; 63 resets = <&cru SRST_CORE1>; 64 }; 65 }; 66 67 amba { 68 compatible = "arm,amba-bus"; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 ranges; 72 73 pdma: pdma@20078000 { 74 compatible = "arm,pl330", "arm,primecell"; 75 reg = <0x20078000 0x4000>; 76 arm,pl330-broken-no-flushp; 77 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 79 #dma-cells = <1>; 80 clocks = <&cru ACLK_DMAC2>; 81 clock-names = "apb_pclk"; 82 }; 83 }; 84 85 xin24m: oscillator { 86 compatible = "fixed-clock"; 87 clock-frequency = <24000000>; 88 clock-output-names = "xin24m"; 89 #clock-cells = <0>; 90 }; 91 92 psci: psci { 93 compatible = "arm,psci-1.0"; 94 method = "smc"; 95 }; 96 97 timer { 98 compatible = "arm,armv7-timer"; 99 arm,cpu-registers-not-fw-configured; 100 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 101 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 104 clock-frequency = <24000000>; 105 }; 106 107 cru: clock-controller@20000000 { 108 compatible = "rockchip,rk3036-cru"; 109 reg = <0x20000000 0x1000>; 110 rockchip,grf = <&grf>; 111 #clock-cells = <1>; 112 #reset-cells = <1>; 113 assigned-clocks = <&cru PLL_GPLL>; 114 assigned-clock-rates = <594000000>; 115 }; 116 117 dmc: dmc@20004000 { 118 compatible = "rockchip,rk3036-dmc", "syscon"; 119 reg = <0x0 0x20004000 0x0 0x1000>; 120 }; 121 122 uart0: serial@20060000 { 123 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 124 reg = <0x20060000 0x100>; 125 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 126 reg-shift = <2>; 127 reg-io-width = <4>; 128 clock-frequency = <24000000>; 129 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 130 clock-names = "baudclk", "apb_pclk"; 131 pinctrl-names = "default"; 132 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 133 }; 134 135 uart1: serial@20064000 { 136 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 137 reg = <0x20064000 0x100>; 138 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 139 reg-shift = <2>; 140 reg-io-width = <4>; 141 clock-frequency = <24000000>; 142 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 143 clock-names = "baudclk", "apb_pclk"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&uart1_xfer>; 146 }; 147 148 uart2: serial@20068000 { 149 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 150 reg = <0x20068000 0x100>; 151 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 152 reg-shift = <2>; 153 reg-io-width = <4>; 154 clock-frequency = <24000000>; 155 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 156 clock-names = "baudclk", "apb_pclk"; 157 pinctrl-names = "default"; 158 pinctrl-0 = <&uart2_xfer>; 159 }; 160 161 pwm0: pwm@20050000 { 162 compatible = "rockchip,rk2928-pwm"; 163 reg = <0x20050000 0x10>; 164 #pwm-cells = <3>; 165 pinctrl-names = "active"; 166 pinctrl-0 = <&pwm0_pin>; 167 clocks = <&cru PCLK_PWM>; 168 clock-names = "pwm"; 169 status = "disabled"; 170 }; 171 172 pwm1: pwm@20050010 { 173 compatible = "rockchip,rk2928-pwm"; 174 reg = <0x20050010 0x10>; 175 #pwm-cells = <3>; 176 pinctrl-names = "active"; 177 pinctrl-0 = <&pwm1_pin>; 178 clocks = <&cru PCLK_PWM>; 179 clock-names = "pwm"; 180 status = "disabled"; 181 }; 182 183 pwm2: pwm@20050020 { 184 compatible = "rockchip,rk2928-pwm"; 185 reg = <0x20050020 0x10>; 186 #pwm-cells = <3>; 187 pinctrl-names = "active"; 188 pinctrl-0 = <&pwm2_pin>; 189 clocks = <&cru PCLK_PWM>; 190 clock-names = "pwm"; 191 status = "disabled"; 192 }; 193 194 pwm3: pwm@20050030 { 195 compatible = "rockchip,rk2928-pwm"; 196 reg = <0x20050030 0x10>; 197 #pwm-cells = <2>; 198 pinctrl-names = "active"; 199 pinctrl-0 = <&pwm3_pin>; 200 clocks = <&cru PCLK_PWM>; 201 clock-names = "pwm"; 202 status = "disabled"; 203 }; 204 205 sram: sram@10080000 { 206 compatible = "rockchip,rk3036-smp-sram", "mmio-sram"; 207 reg = <0x10080000 0x2000>; 208 }; 209 210 gic: interrupt-controller@10139000 { 211 compatible = "arm,gic-400"; 212 interrupt-controller; 213 #interrupt-cells = <3>; 214 #address-cells = <0>; 215 216 reg = <0x10139000 0x1000>, 217 <0x1013a000 0x1000>, 218 <0x1013c000 0x2000>, 219 <0x1013e000 0x2000>; 220 interrupts = <GIC_PPI 9 0xf04>; 221 }; 222 223 grf: syscon@20008000 { 224 compatible = "rockchip,rk3036-grf", "syscon"; 225 reg = <0x20008000 0x1000>; 226 #address-cells = <1>; 227 #size-cells = <1>; 228 229 usb2phy: usb2-phy@17c { 230 compatible = "rockchip,rk3036-usb2phy"; 231 reg = <0x017c 0x0c>; 232 clocks = <&cru SCLK_OTGPHY0>; 233 clock-names = "phyclk"; 234 #clock-cells = <0>; 235 clock-output-names = "usb480m_phy"; 236 status = "disabled"; 237 238 u2phy_otg: otg-port { 239 #phy-cells = <0>; 240 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 243 interrupt-names = "otg-bvalid", "otg-id", 244 "linestate"; 245 status = "disabled"; 246 }; 247 248 u2phy_host: host-port { 249 #phy-cells = <0>; 250 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 251 interrupt-names = "linestate"; 252 status = "disabled"; 253 }; 254 }; 255 }; 256 257 usb_otg: usb@10180000 { 258 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 259 "snps,dwc2"; 260 reg = <0x10180000 0x40000>; 261 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&cru HCLK_OTG0>; 263 clock-names = "otg"; 264 dr_mode = "otg"; 265 g-np-tx-fifo-size = <16>; 266 g-rx-fifo-size = <275>; 267 g-tx-fifo-size = <256 128 128 64 64 32>; 268 g-use-dma; 269 status = "disabled"; 270 }; 271 272 usb_host: usb@101c0000 { 273 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 274 "snps,dwc2"; 275 reg = <0x101c0000 0x40000>; 276 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&cru HCLK_OTG1>; 278 clock-names = "otg"; 279 dr_mode = "host"; 280 status = "disabled"; 281 }; 282 283 emmc: dwmmc@1021c000 { 284 compatible = "rockchip,rk3288-dw-mshc"; 285 clock-frequency = <37500000>; 286 max-frequency = <37500000>; 287 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 288 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 289 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 290 dmas = <&pdma 12>; 291 dma-names = "rx-tx"; 292 fifo-depth = <0x100>; 293 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 294 reg = <0x1021c000 0x4000>; 295 broken-cd; 296 bus-width = <8>; 297 cap-mmc-highspeed; 298 mmc-ddr-1_8v; 299 disable-wp; 300 fifo-mode; 301 non-removable; 302 num-slots = <1>; 303 default-sample-phase = <158>; 304 pinctrl-names = "default"; 305 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 306 }; 307 308 sfc: sfc@102080000 { 309 compatible = "rockchip,rksfc"; 310 reg = <0x10208000 0x4000>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 315 clock-names = "clk_sfc", "hclk_sfc"; 316 status = "disabled"; 317 }; 318 319 sdmmc: dwmmc@10214000 { 320 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; 321 reg = <0x10214000 0x4000>; 322 clock-frequency = <37500000>; 323 max-frequency = <37500000>; 324 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 325 clock-names = "biu", "ciu"; 326 fifo-depth = <0x100>; 327 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 328 status = "disabled"; 329 }; 330 331 nandc: nandc@10500000 { 332 compatible = "rockchip,rk-nandc"; 333 reg = <0x10500000 0x4000>; 334 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 335 nandc_id = <0>; 336 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 337 clock-names = "clk_nandc", "hclk_nandc"; 338 status = "disabled"; 339 }; 340 341 pinctrl: pinctrl { 342 compatible = "rockchip,rk3036-pinctrl"; 343 rockchip,grf = <&grf>; 344 #address-cells = <1>; 345 #size-cells = <1>; 346 ranges; 347 348 gpio0: gpio0@2007c000 { 349 compatible = "rockchip,gpio-bank"; 350 reg = <0x2007c000 0x100>; 351 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&cru PCLK_GPIO0>; 353 354 gpio-controller; 355 #gpio-cells = <2>; 356 357 interrupt-controller; 358 #interrupt-cells = <2>; 359 }; 360 361 gpio1: gpio1@20080000 { 362 compatible = "rockchip,gpio-bank"; 363 reg = <0x20080000 0x100>; 364 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&cru PCLK_GPIO1>; 366 367 gpio-controller; 368 #gpio-cells = <2>; 369 370 interrupt-controller; 371 #interrupt-cells = <2>; 372 }; 373 374 gpio2: gpio2@20084000 { 375 compatible = "rockchip,gpio-bank"; 376 reg = <0x20084000 0x100>; 377 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&cru PCLK_GPIO2>; 379 380 gpio-controller; 381 #gpio-cells = <2>; 382 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 }; 386 387 pcfg_pull_up: pcfg-pull-up { 388 bias-pull-up; 389 }; 390 391 pcfg_pull_down: pcfg-pull-down { 392 bias-pull-down; 393 }; 394 395 pcfg_pull_none: pcfg-pull-none { 396 bias-disable; 397 }; 398 399 emmc { 400 /* 401 * We run eMMC at max speed; bump up drive strength. 402 * We also have external pulls, so disable the internal ones. 403 */ 404 emmc_clk: emmc-clk { 405 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 406 }; 407 408 emmc_cmd: emmc-cmd { 409 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>; 410 }; 411 412 emmc_bus8: emmc-bus8 { 413 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, 414 <1 25 RK_FUNC_2 &pcfg_pull_none>, 415 <1 26 RK_FUNC_2 &pcfg_pull_none>, 416 <1 27 RK_FUNC_2 &pcfg_pull_none>; 417 /* 418 <1 28 RK_FUNC_2 &pcfg_pull_up>, 419 <1 29 RK_FUNC_2 &pcfg_pull_up>, 420 <1 30 RK_FUNC_2 &pcfg_pull_up>, 421 <1 31 RK_FUNC_2 &pcfg_pull_up>; 422 */ 423 }; 424 }; 425 426 uart0 { 427 uart0_xfer: uart0-xfer { 428 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, 429 <0 17 RK_FUNC_1 &pcfg_pull_none>; 430 }; 431 432 uart0_cts: uart0-cts { 433 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 434 }; 435 436 uart0_rts: uart0-rts { 437 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; 438 }; 439 }; 440 441 uart1 { 442 uart1_xfer: uart1-xfer { 443 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, 444 <2 23 RK_FUNC_1 &pcfg_pull_none>; 445 }; 446 /* no rts / cts for uart1 */ 447 }; 448 449 uart2 { 450 uart2_xfer: uart2-xfer { 451 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, 452 <1 19 RK_FUNC_2 &pcfg_pull_none>; 453 }; 454 /* no rts / cts for uart2 */ 455 }; 456 457 pwm0 { 458 pwm0_pin: pwm0-pin { 459 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; 460 }; 461 }; 462 463 pwm1 { 464 pwm1_pin: pwm1-pin { 465 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; 466 }; 467 }; 468 469 pwm2 { 470 pwm2_pin: pwm2-pin { 471 rockchip,pins = <0 1 2 &pcfg_pull_none>; 472 }; 473 }; 474 475 pwm3 { 476 pwm3_pin: pwm3-pin { 477 rockchip,pins = <0 27 1 &pcfg_pull_none>; 478 }; 479 }; 480 481 i2c1 { 482 i2c1_xfer: i2c1-xfer { 483 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, 484 <0 3 RK_FUNC_1 &pcfg_pull_none>; 485 }; 486 }; 487 }; 488 489 i2c1: i2c@20056000 { 490 compatible = "rockchip,rk3288-i2c"; 491 reg = <0x20056000 0x1000>; 492 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 clock-names = "i2c"; 496 clocks = <&cru PCLK_I2C1>; 497 pinctrl-names = "default"; 498 pinctrl-0 = <&i2c1_xfer>; 499 status = "disabled"; 500 }; 501}; 502