1/* 2 * Copyright (c) 2013 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pinctrl/rockchip.h> 10#include <dt-bindings/clock/rk3066a-cru.h> 11#include "rk3xxx.dtsi" 12 13/ { 14 compatible = "rockchip,rk3066a"; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 enable-method = "rockchip,rk3066-smp"; 20 21 cpu0: cpu@0 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-a9"; 24 next-level-cache = <&L2>; 25 reg = <0x0>; 26 operating-points = < 27 /* kHz uV */ 28 1416000 1300000 29 1200000 1175000 30 1008000 1125000 31 816000 1125000 32 600000 1100000 33 504000 1100000 34 312000 1075000 35 >; 36 clock-latency = <40000>; 37 clocks = <&cru ARMCLK>; 38 }; 39 cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a9"; 42 next-level-cache = <&L2>; 43 reg = <0x1>; 44 }; 45 }; 46 47 sram: sram@10080000 { 48 compatible = "mmio-sram"; 49 reg = <0x10080000 0x10000>; 50 #address-cells = <1>; 51 #size-cells = <1>; 52 ranges = <0 0x10080000 0x10000>; 53 54 smp-sram@0 { 55 compatible = "rockchip,rk3066-smp-sram"; 56 reg = <0x0 0x50>; 57 }; 58 }; 59 60 i2s0: i2s@10118000 { 61 compatible = "rockchip,rk3066-i2s"; 62 reg = <0x10118000 0x2000>; 63 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 64 #address-cells = <1>; 65 #size-cells = <0>; 66 pinctrl-names = "default"; 67 pinctrl-0 = <&i2s0_bus>; 68 dmas = <&dmac1_s 4>, <&dmac1_s 5>; 69 dma-names = "tx", "rx"; 70 clock-names = "i2s_hclk", "i2s_clk"; 71 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; 72 rockchip,playback-channels = <8>; 73 rockchip,capture-channels = <2>; 74 status = "disabled"; 75 }; 76 77 i2s1: i2s@1011a000 { 78 compatible = "rockchip,rk3066-i2s"; 79 reg = <0x1011a000 0x2000>; 80 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 81 #address-cells = <1>; 82 #size-cells = <0>; 83 pinctrl-names = "default"; 84 pinctrl-0 = <&i2s1_bus>; 85 dmas = <&dmac1_s 6>, <&dmac1_s 7>; 86 dma-names = "tx", "rx"; 87 clock-names = "i2s_hclk", "i2s_clk"; 88 clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>; 89 rockchip,playback-channels = <2>; 90 rockchip,capture-channels = <2>; 91 status = "disabled"; 92 }; 93 94 i2s2: i2s@1011c000 { 95 compatible = "rockchip,rk3066-i2s"; 96 reg = <0x1011c000 0x2000>; 97 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 98 #address-cells = <1>; 99 #size-cells = <0>; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&i2s2_bus>; 102 dmas = <&dmac1_s 9>, <&dmac1_s 10>; 103 dma-names = "tx", "rx"; 104 clock-names = "i2s_hclk", "i2s_clk"; 105 clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>; 106 rockchip,playback-channels = <2>; 107 rockchip,capture-channels = <2>; 108 status = "disabled"; 109 }; 110 111 nandc: nandc@10500000 { 112 compatible = "rockchip,nandc"; 113 reg = <0x10500000 0x2000>; 114 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 115 clock-names = "hclk"; 116 clocks = <&cru HCLK_NANDC0>; 117 status = "disabled"; 118 }; 119 120 cru: clock-controller@20000000 { 121 compatible = "rockchip,rk3066a-cru"; 122 reg = <0x20000000 0x1000>; 123 rockchip,grf = <&grf>; 124 u-boot,dm-pre-reloc; 125 126 #clock-cells = <1>; 127 #reset-cells = <1>; 128 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, 129 <&cru ACLK_CPU>, <&cru HCLK_CPU>, 130 <&cru PCLK_CPU>, <&cru ACLK_PERI>, 131 <&cru HCLK_PERI>, <&cru PCLK_PERI>; 132 assigned-clock-rates = <400000000>, <594000000>, 133 <300000000>, <150000000>, 134 <75000000>, <300000000>, 135 <150000000>, <75000000>; 136 }; 137 138 timer@2000e000 { 139 compatible = "snps,dw-apb-timer-osc"; 140 reg = <0x2000e000 0x100>; 141 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; 143 clock-names = "timer", "pclk"; 144 }; 145 146 efuse: efuse@20010000 { 147 compatible = "rockchip,rk3066a-efuse"; 148 reg = <0x20010000 0x4000>; 149 #address-cells = <1>; 150 #size-cells = <1>; 151 clocks = <&cru PCLK_EFUSE>; 152 clock-names = "pclk_efuse"; 153 154 cpu_leakage: cpu_leakage@17 { 155 reg = <0x17 0x1>; 156 }; 157 }; 158 159 timer@20038000 { 160 compatible = "snps,dw-apb-timer-osc"; 161 reg = <0x20038000 0x100>; 162 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 163 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; 164 clock-names = "timer", "pclk"; 165 }; 166 167 timer@2003a000 { 168 compatible = "snps,dw-apb-timer-osc"; 169 reg = <0x2003a000 0x100>; 170 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 171 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; 172 clock-names = "timer", "pclk"; 173 }; 174 175 tsadc: tsadc@20060000 { 176 compatible = "rockchip,rk3066-tsadc"; 177 reg = <0x20060000 0x100>; 178 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 179 clock-names = "saradc", "apb_pclk"; 180 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 181 #io-channel-cells = <1>; 182 resets = <&cru SRST_TSADC>; 183 reset-names = "saradc-apb"; 184 status = "disabled"; 185 }; 186 187 usbphy: phy { 188 compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy"; 189 rockchip,grf = <&grf>; 190 #address-cells = <1>; 191 #size-cells = <0>; 192 status = "disabled"; 193 194 usbphy0: usb-phy@17c { 195 #phy-cells = <0>; 196 reg = <0x17c>; 197 clocks = <&cru SCLK_OTGPHY0>; 198 clock-names = "phyclk"; 199 #clock-cells = <0>; 200 }; 201 202 usbphy1: usb-phy@188 { 203 #phy-cells = <0>; 204 reg = <0x188>; 205 clocks = <&cru SCLK_OTGPHY1>; 206 clock-names = "phyclk"; 207 #clock-cells = <0>; 208 }; 209 }; 210 211 pinctrl: pinctrl { 212 compatible = "rockchip,rk3066a-pinctrl"; 213 rockchip,grf = <&grf>; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 ranges; 217 u-boot,dm-pre-reloc; 218 219 gpio0: gpio0@20034000 { 220 compatible = "rockchip,gpio-bank"; 221 reg = <0x20034000 0x100>; 222 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&cru PCLK_GPIO0>; 224 225 gpio-controller; 226 #gpio-cells = <2>; 227 228 interrupt-controller; 229 #interrupt-cells = <2>; 230 }; 231 232 gpio1: gpio1@2003c000 { 233 compatible = "rockchip,gpio-bank"; 234 reg = <0x2003c000 0x100>; 235 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&cru PCLK_GPIO1>; 237 238 gpio-controller; 239 #gpio-cells = <2>; 240 241 interrupt-controller; 242 #interrupt-cells = <2>; 243 }; 244 245 gpio2: gpio2@2003e000 { 246 compatible = "rockchip,gpio-bank"; 247 reg = <0x2003e000 0x100>; 248 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&cru PCLK_GPIO2>; 250 251 gpio-controller; 252 #gpio-cells = <2>; 253 254 interrupt-controller; 255 #interrupt-cells = <2>; 256 }; 257 258 gpio3: gpio3@20080000 { 259 compatible = "rockchip,gpio-bank"; 260 reg = <0x20080000 0x100>; 261 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&cru PCLK_GPIO3>; 263 264 gpio-controller; 265 #gpio-cells = <2>; 266 267 interrupt-controller; 268 #interrupt-cells = <2>; 269 }; 270 271 gpio4: gpio4@20084000 { 272 compatible = "rockchip,gpio-bank"; 273 reg = <0x20084000 0x100>; 274 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&cru PCLK_GPIO4>; 276 277 gpio-controller; 278 #gpio-cells = <2>; 279 280 interrupt-controller; 281 #interrupt-cells = <2>; 282 }; 283 284 gpio6: gpio6@2000a000 { 285 compatible = "rockchip,gpio-bank"; 286 reg = <0x2000a000 0x100>; 287 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&cru PCLK_GPIO6>; 289 290 gpio-controller; 291 #gpio-cells = <2>; 292 293 interrupt-controller; 294 #interrupt-cells = <2>; 295 }; 296 297 pcfg_pull_default: pcfg_pull_default { 298 bias-pull-pin-default; 299 }; 300 301 pcfg_pull_none: pcfg_pull_none { 302 bias-disable; 303 }; 304 305 emac { 306 emac_xfer: emac-xfer { 307 rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */ 308 <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */ 309 <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */ 310 <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */ 311 <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */ 312 <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */ 313 <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */ 314 <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */ 315 }; 316 317 emac_mdio: emac-mdio { 318 rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */ 319 <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */ 320 }; 321 }; 322 323 emmc { 324 emmc_clk: emmc-clk { 325 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>; 326 }; 327 328 emmc_cmd: emmc-cmd { 329 rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>; 330 }; 331 332 emmc_rst: emmc-rst { 333 rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>; 334 }; 335 336 /* 337 * The data pins are shared between nandc and emmc and 338 * not accessible through pinctrl. Also they should've 339 * been already set correctly by firmware, as 340 * flash/emmc is the boot-device. 341 */ 342 }; 343 344 i2c0 { 345 i2c0_xfer: i2c0-xfer { 346 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>, 347 <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>; 348 }; 349 }; 350 351 i2c1 { 352 i2c1_xfer: i2c1-xfer { 353 rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>, 354 <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>; 355 }; 356 }; 357 358 i2c2 { 359 i2c2_xfer: i2c2-xfer { 360 rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>, 361 <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>; 362 }; 363 }; 364 365 i2c3 { 366 i2c3_xfer: i2c3-xfer { 367 rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>, 368 <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>; 369 }; 370 }; 371 372 i2c4 { 373 i2c4_xfer: i2c4-xfer { 374 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>, 375 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>; 376 }; 377 }; 378 379 pwm0 { 380 pwm0_out: pwm0-out { 381 rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>; 382 }; 383 }; 384 385 pwm1 { 386 pwm1_out: pwm1-out { 387 rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>; 388 }; 389 }; 390 391 pwm2 { 392 pwm2_out: pwm2-out { 393 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>; 394 }; 395 }; 396 397 pwm3 { 398 pwm3_out: pwm3-out { 399 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>; 400 }; 401 }; 402 403 spi0 { 404 spi0_clk: spi0-clk { 405 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>; 406 }; 407 spi0_cs0: spi0-cs0 { 408 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>; 409 }; 410 spi0_tx: spi0-tx { 411 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>; 412 }; 413 spi0_rx: spi0-rx { 414 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>; 415 }; 416 spi0_cs1: spi0-cs1 { 417 rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>; 418 }; 419 }; 420 421 spi1 { 422 spi1_clk: spi1-clk { 423 rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>; 424 }; 425 spi1_cs0: spi1-cs0 { 426 rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>; 427 }; 428 spi1_rx: spi1-rx { 429 rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>; 430 }; 431 spi1_tx: spi1-tx { 432 rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>; 433 }; 434 spi1_cs1: spi1-cs1 { 435 rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>; 436 }; 437 }; 438 439 uart0 { 440 uart0_xfer: uart0-xfer { 441 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>, 442 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>; 443 }; 444 445 uart0_cts: uart0-cts { 446 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>; 447 }; 448 449 uart0_rts: uart0-rts { 450 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>; 451 }; 452 }; 453 454 uart1 { 455 uart1_xfer: uart1-xfer { 456 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>, 457 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>; 458 }; 459 460 uart1_cts: uart1-cts { 461 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>; 462 }; 463 464 uart1_rts: uart1-rts { 465 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>; 466 }; 467 }; 468 469 uart2 { 470 uart2_xfer: uart2-xfer { 471 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>, 472 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>; 473 }; 474 /* no rts / cts for uart2 */ 475 }; 476 477 uart3 { 478 uart3_xfer: uart3-xfer { 479 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>, 480 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>; 481 }; 482 483 uart3_cts: uart3-cts { 484 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>; 485 }; 486 487 uart3_rts: uart3-rts { 488 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>; 489 }; 490 }; 491 492 sd0 { 493 sd0_clk: sd0-clk { 494 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>; 495 }; 496 497 sd0_cmd: sd0-cmd { 498 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>; 499 }; 500 501 sd0_cd: sd0-cd { 502 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>; 503 }; 504 505 sd0_wp: sd0-wp { 506 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>; 507 }; 508 509 sd0_bus1: sd0-bus-width1 { 510 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>; 511 }; 512 513 sd0_bus4: sd0-bus-width4 { 514 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>, 515 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>, 516 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>, 517 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>; 518 }; 519 }; 520 521 sd1 { 522 sd1_clk: sd1-clk { 523 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>; 524 }; 525 526 sd1_cmd: sd1-cmd { 527 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>; 528 }; 529 530 sd1_cd: sd1-cd { 531 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>; 532 }; 533 534 sd1_wp: sd1-wp { 535 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>; 536 }; 537 538 sd1_bus1: sd1-bus-width1 { 539 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>; 540 }; 541 542 sd1_bus4: sd1-bus-width4 { 543 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>, 544 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>, 545 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>, 546 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>; 547 }; 548 }; 549 550 i2s0 { 551 i2s0_bus: i2s0-bus { 552 rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>, 553 <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>, 554 <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>, 555 <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>, 556 <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>, 557 <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>, 558 <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>, 559 <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>, 560 <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>; 561 }; 562 }; 563 564 i2s1 { 565 i2s1_bus: i2s1-bus { 566 rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>, 567 <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>, 568 <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>, 569 <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>, 570 <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>, 571 <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>; 572 }; 573 }; 574 575 i2s2 { 576 i2s2_bus: i2s2-bus { 577 rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>, 578 <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>, 579 <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>, 580 <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>, 581 <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>, 582 <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>; 583 }; 584 }; 585 }; 586}; 587 588&grf { 589 compatible = "rockchip,rk3066-grf", "syscon"; 590}; 591 592&i2c0 { 593 pinctrl-names = "default"; 594 pinctrl-0 = <&i2c0_xfer>; 595}; 596 597&i2c1 { 598 pinctrl-names = "default"; 599 pinctrl-0 = <&i2c1_xfer>; 600}; 601 602&i2c2 { 603 pinctrl-names = "default"; 604 pinctrl-0 = <&i2c2_xfer>; 605}; 606 607&i2c3 { 608 pinctrl-names = "default"; 609 pinctrl-0 = <&i2c3_xfer>; 610}; 611 612&i2c4 { 613 pinctrl-names = "default"; 614 pinctrl-0 = <&i2c4_xfer>; 615}; 616 617&mmc0 { 618 clock-frequency = <50000000>; 619 dmas = <&dmac2 1>; 620 dma-names = "rx-tx"; 621 max-frequency = <50000000>; 622 pinctrl-names = "default"; 623 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; 624 u-boot,dm-pre-reloc; 625}; 626 627&mmc1 { 628 dmas = <&dmac2 3>; 629 dma-names = "rx-tx"; 630 pinctrl-names = "default"; 631 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; 632}; 633 634&emmc { 635 dmas = <&dmac2 4>; 636 dma-names = "rx-tx"; 637}; 638 639&pwm0 { 640 pinctrl-names = "active"; 641 pinctrl-0 = <&pwm0_out>; 642}; 643 644&pwm1 { 645 pinctrl-names = "active"; 646 pinctrl-0 = <&pwm1_out>; 647}; 648 649&pwm2 { 650 pinctrl-names = "active"; 651 pinctrl-0 = <&pwm2_out>; 652}; 653 654&pwm3 { 655 pinctrl-names = "active"; 656 pinctrl-0 = <&pwm3_out>; 657}; 658 659&spi0 { 660 pinctrl-names = "default"; 661 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 662}; 663 664&spi1 { 665 pinctrl-names = "default"; 666 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 667}; 668 669&uart0 { 670 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 671 dmas = <&dmac1_s 0>, <&dmac1_s 1>; 672 dma-names = "tx", "rx"; 673 pinctrl-names = "default"; 674 pinctrl-0 = <&uart0_xfer>; 675}; 676 677&uart1 { 678 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 679 dmas = <&dmac1_s 2>, <&dmac1_s 3>; 680 dma-names = "tx", "rx"; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&uart1_xfer>; 683}; 684 685&uart2 { 686 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 687 dmas = <&dmac2 6>, <&dmac2 7>; 688 dma-names = "tx", "rx"; 689 pinctrl-names = "default"; 690 pinctrl-0 = <&uart2_xfer>; 691}; 692 693&uart3 { 694 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 695 dmas = <&dmac2 8>, <&dmac2 9>; 696 dma-names = "tx", "rx"; 697 pinctrl-names = "default"; 698 pinctrl-0 = <&uart3_xfer>; 699}; 700 701&wdt { 702 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; 703}; 704 705&emac { 706 compatible = "rockchip,rk3066-emac"; 707}; 708