1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 4*4882a593Smuzhiyun * Author: Xing Zheng <zhengxing@rock-chips.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* core clocks */ 11*4882a593Smuzhiyun #define PLL_APLL 1 12*4882a593Smuzhiyun #define PLL_DPLL 2 13*4882a593Smuzhiyun #define PLL_GPLL 3 14*4882a593Smuzhiyun #define ARMCLK 4 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* sclk gates (special clocks) */ 17*4882a593Smuzhiyun #define SCLK_GPU 64 18*4882a593Smuzhiyun #define SCLK_SPI 65 19*4882a593Smuzhiyun #define SCLK_SDMMC 68 20*4882a593Smuzhiyun #define SCLK_SDIO 69 21*4882a593Smuzhiyun #define SCLK_EMMC 71 22*4882a593Smuzhiyun #define SCLK_NANDC 76 23*4882a593Smuzhiyun #define SCLK_UART0 77 24*4882a593Smuzhiyun #define SCLK_UART1 78 25*4882a593Smuzhiyun #define SCLK_UART2 79 26*4882a593Smuzhiyun #define SCLK_I2S 82 27*4882a593Smuzhiyun #define SCLK_SPDIF 83 28*4882a593Smuzhiyun #define SCLK_TIMER0 85 29*4882a593Smuzhiyun #define SCLK_TIMER1 86 30*4882a593Smuzhiyun #define SCLK_TIMER2 87 31*4882a593Smuzhiyun #define SCLK_TIMER3 88 32*4882a593Smuzhiyun #define SCLK_OTGPHY0 93 33*4882a593Smuzhiyun #define SCLK_LCDC 100 34*4882a593Smuzhiyun #define SCLK_HDMI 109 35*4882a593Smuzhiyun #define SCLK_HEVC 111 36*4882a593Smuzhiyun #define SCLK_I2S_OUT 113 37*4882a593Smuzhiyun #define SCLK_SDMMC_DRV 114 38*4882a593Smuzhiyun #define SCLK_SDIO_DRV 115 39*4882a593Smuzhiyun #define SCLK_EMMC_DRV 117 40*4882a593Smuzhiyun #define SCLK_SDMMC_SAMPLE 118 41*4882a593Smuzhiyun #define SCLK_SDIO_SAMPLE 119 42*4882a593Smuzhiyun #define SCLK_EMMC_SAMPLE 121 43*4882a593Smuzhiyun #define SCLK_PVTM_CORE 123 44*4882a593Smuzhiyun #define SCLK_PVTM_GPU 124 45*4882a593Smuzhiyun #define SCLK_PVTM_VIDEO 125 46*4882a593Smuzhiyun #define SCLK_I2S_FRAC 126 47*4882a593Smuzhiyun #define SCLK_I2S_PRE 127 48*4882a593Smuzhiyun #define SCLK_MAC 151 49*4882a593Smuzhiyun #define SCLK_MACREF 152 50*4882a593Smuzhiyun #define SCLK_MACPLL 153 51*4882a593Smuzhiyun #define SCLK_SFC 160 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* aclk gates */ 54*4882a593Smuzhiyun #define ACLK_DMAC2 194 55*4882a593Smuzhiyun #define ACLK_LCDC 197 56*4882a593Smuzhiyun #define ACLK_VIO 203 57*4882a593Smuzhiyun #define ACLK_VCODEC 208 58*4882a593Smuzhiyun #define ACLK_CPU 209 59*4882a593Smuzhiyun #define ACLK_PERI 210 60*4882a593Smuzhiyun #define ACLK_HEVC 211 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* pclk gates */ 63*4882a593Smuzhiyun #define PCLK_GPIO0 320 64*4882a593Smuzhiyun #define PCLK_GPIO1 321 65*4882a593Smuzhiyun #define PCLK_GPIO2 322 66*4882a593Smuzhiyun #define PCLK_GRF 329 67*4882a593Smuzhiyun #define PCLK_I2C0 332 68*4882a593Smuzhiyun #define PCLK_I2C1 333 69*4882a593Smuzhiyun #define PCLK_I2C2 334 70*4882a593Smuzhiyun #define PCLK_SPI 338 71*4882a593Smuzhiyun #define PCLK_UART0 341 72*4882a593Smuzhiyun #define PCLK_UART1 342 73*4882a593Smuzhiyun #define PCLK_UART2 343 74*4882a593Smuzhiyun #define PCLK_PWM 350 75*4882a593Smuzhiyun #define PCLK_TIMER 353 76*4882a593Smuzhiyun #define PCLK_HDMI 360 77*4882a593Smuzhiyun #define PCLK_CPU 362 78*4882a593Smuzhiyun #define PCLK_PERI 363 79*4882a593Smuzhiyun #define PCLK_DDRUPCTL 364 80*4882a593Smuzhiyun #define PCLK_WDT 368 81*4882a593Smuzhiyun #define PCLK_ACODEC 369 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* hclk gates */ 84*4882a593Smuzhiyun #define HCLK_OTG0 449 85*4882a593Smuzhiyun #define HCLK_OTG1 450 86*4882a593Smuzhiyun #define HCLK_NANDC 453 87*4882a593Smuzhiyun #define HCLK_SFC 454 88*4882a593Smuzhiyun #define HCLK_SDMMC 456 89*4882a593Smuzhiyun #define HCLK_SDIO 457 90*4882a593Smuzhiyun #define HCLK_EMMC 459 91*4882a593Smuzhiyun #define HCLK_MAC 460 92*4882a593Smuzhiyun #define HCLK_I2S 462 93*4882a593Smuzhiyun #define HCLK_LCDC 465 94*4882a593Smuzhiyun #define HCLK_ROM 467 95*4882a593Smuzhiyun #define HCLK_VIO_BUS 472 96*4882a593Smuzhiyun #define HCLK_VCODEC 476 97*4882a593Smuzhiyun #define HCLK_CPU 477 98*4882a593Smuzhiyun #define HCLK_PERI 478 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define CLK_NR_CLKS (HCLK_PERI + 1) 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* soft-reset indices */ 103*4882a593Smuzhiyun #define SRST_CORE0 0 104*4882a593Smuzhiyun #define SRST_CORE1 1 105*4882a593Smuzhiyun #define SRST_CORE0_DBG 4 106*4882a593Smuzhiyun #define SRST_CORE1_DBG 5 107*4882a593Smuzhiyun #define SRST_CORE0_POR 8 108*4882a593Smuzhiyun #define SRST_CORE1_POR 9 109*4882a593Smuzhiyun #define SRST_L2C 12 110*4882a593Smuzhiyun #define SRST_TOPDBG 13 111*4882a593Smuzhiyun #define SRST_STRC_SYS_A 14 112*4882a593Smuzhiyun #define SRST_PD_CORE_NIU 15 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define SRST_TIMER2 16 115*4882a593Smuzhiyun #define SRST_CPUSYS_H 17 116*4882a593Smuzhiyun #define SRST_AHB2APB_H 19 117*4882a593Smuzhiyun #define SRST_TIMER3 20 118*4882a593Smuzhiyun #define SRST_INTMEM 21 119*4882a593Smuzhiyun #define SRST_ROM 22 120*4882a593Smuzhiyun #define SRST_PERI_NIU 23 121*4882a593Smuzhiyun #define SRST_I2S 24 122*4882a593Smuzhiyun #define SRST_DDR_PLL 25 123*4882a593Smuzhiyun #define SRST_GPU_DLL 26 124*4882a593Smuzhiyun #define SRST_TIMER0 27 125*4882a593Smuzhiyun #define SRST_TIMER1 28 126*4882a593Smuzhiyun #define SRST_CORE_DLL 29 127*4882a593Smuzhiyun #define SRST_EFUSE_P 30 128*4882a593Smuzhiyun #define SRST_ACODEC_P 31 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define SRST_GPIO0 32 131*4882a593Smuzhiyun #define SRST_GPIO1 33 132*4882a593Smuzhiyun #define SRST_GPIO2 34 133*4882a593Smuzhiyun #define SRST_UART0 39 134*4882a593Smuzhiyun #define SRST_UART1 40 135*4882a593Smuzhiyun #define SRST_UART2 41 136*4882a593Smuzhiyun #define SRST_I2C0 43 137*4882a593Smuzhiyun #define SRST_I2C1 44 138*4882a593Smuzhiyun #define SRST_I2C2 45 139*4882a593Smuzhiyun #define SRST_SFC 47 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define SRST_PWM0 48 142*4882a593Smuzhiyun #define SRST_DAP 51 143*4882a593Smuzhiyun #define SRST_DAP_SYS 52 144*4882a593Smuzhiyun #define SRST_GRF 55 145*4882a593Smuzhiyun #define SRST_PERIPHSYS_A 57 146*4882a593Smuzhiyun #define SRST_PERIPHSYS_H 58 147*4882a593Smuzhiyun #define SRST_PERIPHSYS_P 59 148*4882a593Smuzhiyun #define SRST_CPU_PERI 61 149*4882a593Smuzhiyun #define SRST_EMEM_PERI 62 150*4882a593Smuzhiyun #define SRST_USB_PERI 63 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #define SRST_DMA2 64 153*4882a593Smuzhiyun #define SRST_MAC 66 154*4882a593Smuzhiyun #define SRST_NANDC 68 155*4882a593Smuzhiyun #define SRST_USBOTG0 69 156*4882a593Smuzhiyun #define SRST_OTGC0 71 157*4882a593Smuzhiyun #define SRST_USBOTG1 72 158*4882a593Smuzhiyun #define SRST_OTGC1 74 159*4882a593Smuzhiyun #define SRST_DDRMSCH 79 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #define SRST_MMC0 81 162*4882a593Smuzhiyun #define SRST_SDIO 82 163*4882a593Smuzhiyun #define SRST_EMMC 83 164*4882a593Smuzhiyun #define SRST_SPI0 84 165*4882a593Smuzhiyun #define SRST_WDT 86 166*4882a593Smuzhiyun #define SRST_DDRPHY 88 167*4882a593Smuzhiyun #define SRST_DDRPHY_P 89 168*4882a593Smuzhiyun #define SRST_DDRCTRL 90 169*4882a593Smuzhiyun #define SRST_DDRCTRL_P 91 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun #define SRST_HDMI_P 96 172*4882a593Smuzhiyun #define SRST_VIO_BUS_H 99 173*4882a593Smuzhiyun #define SRST_UTMI0 103 174*4882a593Smuzhiyun #define SRST_UTMI1 104 175*4882a593Smuzhiyun #define SRST_USBPOR 105 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun #define SRST_VCODEC_A 112 178*4882a593Smuzhiyun #define SRST_VCODEC_H 113 179*4882a593Smuzhiyun #define SRST_VIO1_A 114 180*4882a593Smuzhiyun #define SRST_HEVC 115 181*4882a593Smuzhiyun #define SRST_VCODEC_NIU_A 116 182*4882a593Smuzhiyun #define SRST_LCDC1_A 117 183*4882a593Smuzhiyun #define SRST_LCDC1_H 118 184*4882a593Smuzhiyun #define SRST_LCDC1_D 119 185*4882a593Smuzhiyun #define SRST_GPU 120 186*4882a593Smuzhiyun #define SRST_GPU_NIU_A 122 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun #define SRST_DBG_P 131 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun #endif 191