1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2013 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/clock/rk3066a-cru.h> 10#include <dt-bindings/power/rk3066-power.h> 11#include "rk3xxx.dtsi" 12 13/ { 14 compatible = "rockchip,rk3066a"; 15 16 aliases { 17 gpio0 = &gpio0; 18 gpio1 = &gpio1; 19 gpio2 = &gpio2; 20 gpio3 = &gpio3; 21 gpio4 = &gpio4; 22 gpio6 = &gpio6; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 enable-method = "rockchip,rk3066-smp"; 29 30 cpu0: cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a9"; 33 next-level-cache = <&L2>; 34 reg = <0x0>; 35 operating-points-v2 = <&cpu0_opp_table>; 36 clocks = <&cru ARMCLK>; 37 }; 38 cpu1: cpu@1 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a9"; 41 next-level-cache = <&L2>; 42 reg = <0x1>; 43 operating-points-v2 = <&cpu0_opp_table>; 44 }; 45 }; 46 47 cpu0_opp_table: opp_table0 { 48 compatible = "operating-points-v2"; 49 opp-shared; 50 51 opp-312000000 { 52 opp-hz = /bits/ 64 <312000000>; 53 opp-microvolt = <1075000 1075000 1125000>; 54 clock-latency-ns = <40000>; 55 status = "disabled"; 56 }; 57 opp-504000000 { 58 opp-hz = /bits/ 64 <504000000>; 59 opp-microvolt = <1100000 1100000 1125000>; 60 clock-latency-ns = <40000>; 61 status = "disabled"; 62 }; 63 opp-816000000 { 64 opp-hz = /bits/ 64 <816000000>; 65 opp-microvolt = <1125000 1125000 1125000>; 66 clock-latency-ns = <40000>; 67 status = "disabled"; 68 }; 69 opp-1008000000 { 70 opp-hz = /bits/ 64 <1008000000>; 71 opp-microvolt = <1125000 1125000 1125000>; 72 clock-latency-ns = <40000>; 73 status = "disabled"; 74 }; 75 }; 76 77 display-subsystem { 78 compatible = "rockchip,display-subsystem"; 79 ports = <&vop0_out>, <&vop1_out>; 80 }; 81 82 sram: sram@10080000 { 83 compatible = "mmio-sram"; 84 reg = <0x10080000 0x10000>; 85 #address-cells = <1>; 86 #size-cells = <1>; 87 ranges = <0 0x10080000 0x10000>; 88 89 smp-sram@0 { 90 compatible = "rockchip,rk3066-smp-sram"; 91 reg = <0x0 0x50>; 92 }; 93 }; 94 95 gpu: gpu@10090000 { 96 compatible = "arm,mali400"; 97 98 reg = <0x10091000 0x200>, 99 <0x10090000 0x100>, 100 <0x10093000 0x100>, 101 <0x10098000 0x1100>, 102 <0x10094000 0x100>, 103 <0x1009A000 0x1100>, 104 <0x10095000 0x100>, 105 <0x1009C000 0x1100>, 106 <0x10096000 0x100>, 107 <0x1009E000 0x1100>, 108 <0x10097000 0x100>; 109 reg-names = "Mali_L2", 110 "Mali_GP", 111 "Mali_GP_MMU", 112 "Mali_PP0", 113 "Mali_PP0_MMU", 114 "Mali_PP1", 115 "Mali_PP1_MMU", 116 "Mali_PP2", 117 "Mali_PP2_MMU", 118 "Mali_PP3", 119 "Mali_PP3_MMU"; 120 121 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 131 interrupt-names = "Mali_GP_IRQ", 132 "Mali_GP_MMU_IRQ", 133 "Mali_PP0_IRQ", 134 "Mali_PP0_MMU_IRQ", 135 "Mali_PP1_IRQ", 136 "Mali_PP1_MMU_IRQ", 137 "Mali_PP2_IRQ", 138 "Mali_PP2_MMU_IRQ", 139 "Mali_PP3_IRQ", 140 "Mali_PP3_MMU_IRQ"; 141 clocks = <&cru ACLK_GPU>; 142 clock-names = "clk_mali"; 143 144 operating-points-v2 = <&gpu_opp_table>; 145 status = "disabled"; 146 147 gpu_power_model: power_model { 148 compatible = "arm,mali-simple-power-model"; 149 voltage = <950>; 150 frequency = <500>; 151 static-power = <300>; 152 dynamic-power = <396>; 153 ts = <32000 4700 (-80) 2>; 154 thermal-zone = "gpu-thermal"; 155 }; 156 }; 157 158 gpu_opp_table: opp-table2 { 159 compatible = "operating-points-v2"; 160 opp-300000000 { 161 opp-hz = /bits/ 64 <300000000>; 162 opp-microvolt = <1050000>; 163 status = "disabled"; 164 }; 165 opp-400000000 { 166 opp-hz = /bits/ 64 <400000000>; 167 opp-microvolt = <1275000>; 168 status = "disabled"; 169 }; 170 }; 171 172 vop0: vop@1010c000 { 173 compatible = "rockchip,rk3066-vop"; 174 reg = <0x1010c000 0x19c>; 175 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 176 clocks = <&cru ACLK_LCDC0>, 177 <&cru DCLK_LCDC0>, 178 <&cru HCLK_LCDC0>; 179 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 180 power-domains = <&power RK3066_PD_VIO>; 181 resets = <&cru SRST_LCDC0_AXI>, 182 <&cru SRST_LCDC0_AHB>, 183 <&cru SRST_LCDC0_DCLK>; 184 reset-names = "axi", "ahb", "dclk"; 185 status = "disabled"; 186 187 vop0_out: port { 188 #address-cells = <1>; 189 #size-cells = <0>; 190 191 vop0_out_hdmi: endpoint@0 { 192 reg = <0>; 193 remote-endpoint = <&hdmi_in_vop0>; 194 }; 195 }; 196 }; 197 198 vop1: vop@1010e000 { 199 compatible = "rockchip,rk3066-vop"; 200 reg = <0x1010e000 0x19c>; 201 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&cru ACLK_LCDC1>, 203 <&cru DCLK_LCDC1>, 204 <&cru HCLK_LCDC1>; 205 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 206 power-domains = <&power RK3066_PD_VIO>; 207 resets = <&cru SRST_LCDC1_AXI>, 208 <&cru SRST_LCDC1_AHB>, 209 <&cru SRST_LCDC1_DCLK>; 210 reset-names = "axi", "ahb", "dclk"; 211 status = "disabled"; 212 213 vop1_out: port { 214 #address-cells = <1>; 215 #size-cells = <0>; 216 217 vop1_out_hdmi: endpoint@0 { 218 reg = <0>; 219 remote-endpoint = <&hdmi_in_vop1>; 220 }; 221 }; 222 }; 223 224 hdmi: hdmi@10116000 { 225 compatible = "rockchip,rk3066-hdmi"; 226 reg = <0x10116000 0x2000>; 227 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&cru HCLK_HDMI>; 229 clock-names = "hclk"; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; 232 power-domains = <&power RK3066_PD_VIO>; 233 rockchip,grf = <&grf>; 234 status = "disabled"; 235 236 ports { 237 #address-cells = <1>; 238 #size-cells = <0>; 239 240 hdmi_in: port@0 { 241 reg = <0>; 242 #address-cells = <1>; 243 #size-cells = <0>; 244 245 hdmi_in_vop0: endpoint@0 { 246 reg = <0>; 247 remote-endpoint = <&vop0_out_hdmi>; 248 }; 249 250 hdmi_in_vop1: endpoint@1 { 251 reg = <1>; 252 remote-endpoint = <&vop1_out_hdmi>; 253 }; 254 }; 255 256 hdmi_out: port@1 { 257 reg = <1>; 258 }; 259 }; 260 }; 261 262 i2s0: i2s@10118000 { 263 compatible = "rockchip,rk3066-i2s"; 264 reg = <0x10118000 0x2000>; 265 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 266 pinctrl-names = "default"; 267 pinctrl-0 = <&i2s0_bus>; 268 dmas = <&dmac1_s 4>, <&dmac1_s 5>; 269 dma-names = "tx", "rx"; 270 clock-names = "i2s_hclk", "i2s_clk"; 271 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S0>; 272 resets = <&cru SRST_I2S0>; 273 reset-names = "reset-m"; 274 rockchip,playback-channels = <8>; 275 rockchip,capture-channels = <2>; 276 #sound-dai-cells = <0>; 277 status = "disabled"; 278 }; 279 280 i2s1: i2s@1011a000 { 281 compatible = "rockchip,rk3066-i2s"; 282 reg = <0x1011a000 0x2000>; 283 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&i2s1_bus>; 286 dmas = <&dmac1_s 6>, <&dmac1_s 7>; 287 dma-names = "tx", "rx"; 288 clock-names = "i2s_hclk", "i2s_clk"; 289 clocks = <&cru HCLK_I2S0_2CH>, <&cru SCLK_I2S1>; 290 resets = <&cru SRST_I2S1>; 291 reset-names = "reset-m"; 292 rockchip,playback-channels = <2>; 293 rockchip,capture-channels = <2>; 294 #sound-dai-cells = <0>; 295 status = "disabled"; 296 }; 297 298 i2s2: i2s@1011c000 { 299 compatible = "rockchip,rk3066-i2s"; 300 reg = <0x1011c000 0x2000>; 301 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&i2s2_bus>; 304 dmas = <&dmac1_s 9>, <&dmac1_s 10>; 305 dma-names = "tx", "rx"; 306 clock-names = "i2s_hclk", "i2s_clk"; 307 clocks = <&cru HCLK_I2S1_2CH>, <&cru SCLK_I2S2>; 308 resets = <&cru SRST_I2S2>; 309 reset-names = "reset-m"; 310 rockchip,playback-channels = <2>; 311 rockchip,capture-channels = <2>; 312 #sound-dai-cells = <0>; 313 status = "disabled"; 314 }; 315 316 cru: clock-controller@20000000 { 317 compatible = "rockchip,rk3066a-cru"; 318 reg = <0x20000000 0x1000>; 319 rockchip,grf = <&grf>; 320 321 #clock-cells = <1>; 322 #reset-cells = <1>; 323 324 assigned-clocks = 325 <&cru PLL_GPLL>, <&cru ARMCLK>, 326 <&cru PLL_CPLL>, <&cru ACLK_PERI>, 327 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 328 <&cru ACLK_CPU>, <&cru HCLK_CPU>, 329 <&cru PCLK_CPU>; 330 assigned-clock-rates = 331 <594000000>, <816000000>, 332 <400000000>, <150000000>, 333 <75000000>, <75000000>, 334 <150000000>, <75000000>, 335 <75000000>; 336 }; 337 338 timer@2000e000 { 339 compatible = "snps,dw-apb-timer-osc"; 340 reg = <0x2000e000 0x100>; 341 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; 343 clock-names = "timer", "pclk"; 344 }; 345 346 efuse: efuse@20010000 { 347 compatible = "rockchip,rk3066a-efuse"; 348 reg = <0x20010000 0x4000>; 349 #address-cells = <1>; 350 #size-cells = <1>; 351 clocks = <&cru PCLK_EFUSE>; 352 clock-names = "pclk_efuse"; 353 354 cpu_leakage: cpu_leakage@17 { 355 reg = <0x17 0x1>; 356 }; 357 }; 358 359 timer@20038000 { 360 compatible = "snps,dw-apb-timer-osc"; 361 reg = <0x20038000 0x100>; 362 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; 364 clock-names = "timer", "pclk"; 365 }; 366 367 timer@2003a000 { 368 compatible = "snps,dw-apb-timer-osc"; 369 reg = <0x2003a000 0x100>; 370 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; 372 clock-names = "timer", "pclk"; 373 }; 374 375 tsadc: tsadc@20060000 { 376 compatible = "rockchip,rk3066-tsadc"; 377 reg = <0x20060000 0x100>; 378 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 379 clock-names = "saradc", "apb_pclk"; 380 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 381 #io-channel-cells = <1>; 382 resets = <&cru SRST_TSADC>; 383 reset-names = "saradc-apb"; 384 status = "disabled"; 385 }; 386 387 usbphy: phy { 388 compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy"; 389 rockchip,grf = <&grf>; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 status = "disabled"; 393 394 usbphy0: usb-phy@17c { 395 #phy-cells = <0>; 396 reg = <0x17c>; 397 clocks = <&cru SCLK_OTGPHY0>; 398 clock-names = "phyclk"; 399 #clock-cells = <0>; 400 }; 401 402 usbphy1: usb-phy@188 { 403 #phy-cells = <0>; 404 reg = <0x188>; 405 clocks = <&cru SCLK_OTGPHY1>; 406 clock-names = "phyclk"; 407 #clock-cells = <0>; 408 }; 409 }; 410 411 pinctrl: pinctrl { 412 compatible = "rockchip,rk3066a-pinctrl"; 413 rockchip,grf = <&grf>; 414 #address-cells = <1>; 415 #size-cells = <1>; 416 ranges; 417 418 gpio0: gpio0@20034000 { 419 compatible = "rockchip,gpio-bank"; 420 reg = <0x20034000 0x100>; 421 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 422 clock-names = "bus"; 423 clocks = <&cru PCLK_GPIO0>; 424 425 gpio-controller; 426 #gpio-cells = <2>; 427 428 interrupt-controller; 429 #interrupt-cells = <2>; 430 }; 431 432 gpio1: gpio1@2003c000 { 433 compatible = "rockchip,gpio-bank"; 434 reg = <0x2003c000 0x100>; 435 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 436 clock-names = "bus"; 437 clocks = <&cru PCLK_GPIO1>; 438 439 gpio-controller; 440 #gpio-cells = <2>; 441 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 }; 445 446 gpio2: gpio2@2003e000 { 447 compatible = "rockchip,gpio-bank"; 448 reg = <0x2003e000 0x100>; 449 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 450 clock-names = "bus"; 451 clocks = <&cru PCLK_GPIO2>; 452 453 gpio-controller; 454 #gpio-cells = <2>; 455 456 interrupt-controller; 457 #interrupt-cells = <2>; 458 }; 459 460 gpio3: gpio3@20080000 { 461 compatible = "rockchip,gpio-bank"; 462 reg = <0x20080000 0x100>; 463 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 464 clock-names = "bus"; 465 clocks = <&cru PCLK_GPIO3>; 466 467 gpio-controller; 468 #gpio-cells = <2>; 469 470 interrupt-controller; 471 #interrupt-cells = <2>; 472 }; 473 474 gpio4: gpio4@20084000 { 475 compatible = "rockchip,gpio-bank"; 476 reg = <0x20084000 0x100>; 477 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 478 clock-names = "bus"; 479 clocks = <&cru PCLK_GPIO4>; 480 481 gpio-controller; 482 #gpio-cells = <2>; 483 484 interrupt-controller; 485 #interrupt-cells = <2>; 486 }; 487 488 gpio6: gpio6@2000a000 { 489 compatible = "rockchip,gpio-bank"; 490 reg = <0x2000a000 0x100>; 491 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 492 clock-names = "bus"; 493 clocks = <&cru PCLK_GPIO6>; 494 495 gpio-controller; 496 #gpio-cells = <2>; 497 498 interrupt-controller; 499 #interrupt-cells = <2>; 500 }; 501 502 pcfg_pull_default: pcfg_pull_default { 503 bias-pull-pin-default; 504 }; 505 506 pcfg_pull_none: pcfg_pull_none { 507 bias-disable; 508 }; 509 510 emac { 511 emac_xfer: emac-xfer { 512 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */ 513 <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */ 514 <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */ 515 <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */ 516 <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */ 517 <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */ 518 <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */ 519 <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */ 520 }; 521 522 emac_mdio: emac-mdio { 523 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */ 524 <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */ 525 }; 526 }; 527 528 emmc { 529 emmc_clk: emmc-clk { 530 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>; 531 }; 532 533 emmc_cmd: emmc-cmd { 534 rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>; 535 }; 536 537 emmc_rst: emmc-rst { 538 rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>; 539 }; 540 541 /* 542 * The data pins are shared between nandc and emmc and 543 * not accessible through pinctrl. Also they should've 544 * been already set correctly by firmware, as 545 * flash/emmc is the boot-device. 546 */ 547 }; 548 549 hdmi { 550 hdmi_hpd: hdmi-hpd { 551 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; 552 }; 553 554 hdmii2c_xfer: hdmii2c-xfer { 555 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, 556 <0 RK_PA2 1 &pcfg_pull_none>; 557 }; 558 }; 559 560 i2c0 { 561 i2c0_xfer: i2c0-xfer { 562 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>, 563 <2 RK_PD5 1 &pcfg_pull_none>; 564 }; 565 }; 566 567 i2c1 { 568 i2c1_xfer: i2c1-xfer { 569 rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>, 570 <2 RK_PD7 1 &pcfg_pull_none>; 571 }; 572 }; 573 574 i2c2 { 575 i2c2_xfer: i2c2-xfer { 576 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>, 577 <3 RK_PA1 1 &pcfg_pull_none>; 578 }; 579 }; 580 581 i2c3 { 582 i2c3_xfer: i2c3-xfer { 583 rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>, 584 <3 RK_PA3 2 &pcfg_pull_none>; 585 }; 586 }; 587 588 i2c4 { 589 i2c4_xfer: i2c4-xfer { 590 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, 591 <3 RK_PA5 1 &pcfg_pull_none>; 592 }; 593 }; 594 595 pwm0 { 596 pwm0_out: pwm0-out { 597 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 598 }; 599 }; 600 601 pwm1 { 602 pwm1_out: pwm1-out { 603 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; 604 }; 605 }; 606 607 pwm2 { 608 pwm2_out: pwm2-out { 609 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 610 }; 611 }; 612 613 pwm3 { 614 pwm3_out: pwm3-out { 615 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; 616 }; 617 }; 618 619 spi0 { 620 spi0_clk: spi0-clk { 621 rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>; 622 }; 623 spi0_cs0: spi0-cs0 { 624 rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>; 625 }; 626 spi0_tx: spi0-tx { 627 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>; 628 }; 629 spi0_rx: spi0-rx { 630 rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>; 631 }; 632 spi0_cs1: spi0-cs1 { 633 rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>; 634 }; 635 }; 636 637 spi1 { 638 spi1_clk: spi1-clk { 639 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>; 640 }; 641 spi1_cs0: spi1-cs0 { 642 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>; 643 }; 644 spi1_rx: spi1-rx { 645 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>; 646 }; 647 spi1_tx: spi1-tx { 648 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>; 649 }; 650 spi1_cs1: spi1-cs1 { 651 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>; 652 }; 653 }; 654 655 uart0 { 656 uart0_xfer: uart0-xfer { 657 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, 658 <1 RK_PA1 1 &pcfg_pull_default>; 659 }; 660 661 uart0_cts: uart0-cts { 662 rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>; 663 }; 664 665 uart0_rts: uart0-rts { 666 rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>; 667 }; 668 }; 669 670 uart1 { 671 uart1_xfer: uart1-xfer { 672 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>, 673 <1 RK_PA5 1 &pcfg_pull_default>; 674 }; 675 676 uart1_cts: uart1-cts { 677 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>; 678 }; 679 680 uart1_rts: uart1-rts { 681 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 682 }; 683 }; 684 685 uart2 { 686 uart2_xfer: uart2-xfer { 687 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, 688 <1 RK_PB1 1 &pcfg_pull_default>; 689 }; 690 /* no rts / cts for uart2 */ 691 }; 692 693 uart3 { 694 uart3_xfer: uart3-xfer { 695 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>, 696 <3 RK_PD4 1 &pcfg_pull_default>; 697 }; 698 699 uart3_cts: uart3-cts { 700 rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>; 701 }; 702 703 uart3_rts: uart3-rts { 704 rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>; 705 }; 706 }; 707 708 sd0 { 709 sd0_clk: sd0-clk { 710 rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>; 711 }; 712 713 sd0_cmd: sd0-cmd { 714 rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>; 715 }; 716 717 sd0_cd: sd0-cd { 718 rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>; 719 }; 720 721 sd0_wp: sd0-wp { 722 rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>; 723 }; 724 725 sd0_bus1: sd0-bus-width1 { 726 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>; 727 }; 728 729 sd0_bus4: sd0-bus-width4 { 730 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>, 731 <3 RK_PB3 1 &pcfg_pull_default>, 732 <3 RK_PB4 1 &pcfg_pull_default>, 733 <3 RK_PB5 1 &pcfg_pull_default>; 734 }; 735 }; 736 737 sd1 { 738 sd1_clk: sd1-clk { 739 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>; 740 }; 741 742 sd1_cmd: sd1-cmd { 743 rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>; 744 }; 745 746 sd1_cd: sd1-cd { 747 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>; 748 }; 749 750 sd1_wp: sd1-wp { 751 rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>; 752 }; 753 754 sd1_bus1: sd1-bus-width1 { 755 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>; 756 }; 757 758 sd1_bus4: sd1-bus-width4 { 759 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>, 760 <3 RK_PC2 1 &pcfg_pull_default>, 761 <3 RK_PC3 1 &pcfg_pull_default>, 762 <3 RK_PC4 1 &pcfg_pull_default>; 763 }; 764 }; 765 766 i2s0 { 767 i2s0_bus: i2s0-bus { 768 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>, 769 <0 RK_PB0 1 &pcfg_pull_default>, 770 <0 RK_PB1 1 &pcfg_pull_default>, 771 <0 RK_PB2 1 &pcfg_pull_default>, 772 <0 RK_PB3 1 &pcfg_pull_default>, 773 <0 RK_PB4 1 &pcfg_pull_default>, 774 <0 RK_PB5 1 &pcfg_pull_default>, 775 <0 RK_PB6 1 &pcfg_pull_default>, 776 <0 RK_PB7 1 &pcfg_pull_default>; 777 }; 778 }; 779 780 i2s1 { 781 i2s1_bus: i2s1-bus { 782 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, 783 <0 RK_PC1 1 &pcfg_pull_default>, 784 <0 RK_PC2 1 &pcfg_pull_default>, 785 <0 RK_PC3 1 &pcfg_pull_default>, 786 <0 RK_PC4 1 &pcfg_pull_default>, 787 <0 RK_PC5 1 &pcfg_pull_default>; 788 }; 789 }; 790 791 i2s2 { 792 i2s2_bus: i2s2-bus { 793 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>, 794 <0 RK_PD1 1 &pcfg_pull_default>, 795 <0 RK_PD2 1 &pcfg_pull_default>, 796 <0 RK_PD3 1 &pcfg_pull_default>, 797 <0 RK_PD4 1 &pcfg_pull_default>, 798 <0 RK_PD5 1 &pcfg_pull_default>; 799 }; 800 }; 801 }; 802}; 803 804&gpu { 805 compatible = "rockchip,rk3066-mali", "arm,mali-400"; 806 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 816 interrupt-names = "gp", 817 "gpmmu", 818 "pp0", 819 "ppmmu0", 820 "pp1", 821 "ppmmu1", 822 "pp2", 823 "ppmmu2", 824 "pp3", 825 "ppmmu3"; 826 power-domains = <&power RK3066_PD_GPU>; 827}; 828 829&i2c0 { 830 pinctrl-names = "default"; 831 pinctrl-0 = <&i2c0_xfer>; 832}; 833 834&i2c1 { 835 pinctrl-names = "default"; 836 pinctrl-0 = <&i2c1_xfer>; 837}; 838 839&i2c2 { 840 pinctrl-names = "default"; 841 pinctrl-0 = <&i2c2_xfer>; 842}; 843 844&i2c3 { 845 pinctrl-names = "default"; 846 pinctrl-0 = <&i2c3_xfer>; 847}; 848 849&i2c4 { 850 pinctrl-names = "default"; 851 pinctrl-0 = <&i2c4_xfer>; 852}; 853 854&mmc0 { 855 clock-frequency = <50000000>; 856 dmas = <&dmac2 1>; 857 dma-names = "rx-tx"; 858 max-frequency = <50000000>; 859 pinctrl-names = "default"; 860 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; 861}; 862 863&mmc1 { 864 dmas = <&dmac2 3>; 865 dma-names = "rx-tx"; 866 pinctrl-names = "default"; 867 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; 868}; 869 870&emmc { 871 dmas = <&dmac2 4>; 872 dma-names = "rx-tx"; 873}; 874 875&pmu { 876 power: power-controller { 877 compatible = "rockchip,rk3066-power-controller"; 878 #power-domain-cells = <1>; 879 #address-cells = <1>; 880 #size-cells = <0>; 881 882 power-domain@RK3066_PD_VIO { 883 reg = <RK3066_PD_VIO>; 884 clocks = <&cru ACLK_LCDC0>, 885 <&cru ACLK_LCDC1>, 886 <&cru DCLK_LCDC0>, 887 <&cru DCLK_LCDC1>, 888 <&cru HCLK_LCDC0>, 889 <&cru HCLK_LCDC1>, 890 <&cru SCLK_CIF1>, 891 <&cru ACLK_CIF1>, 892 <&cru HCLK_CIF1>, 893 <&cru SCLK_CIF0>, 894 <&cru ACLK_CIF0>, 895 <&cru HCLK_CIF0>, 896 <&cru HCLK_HDMI>, 897 <&cru ACLK_IPP>, 898 <&cru HCLK_IPP>, 899 <&cru ACLK_RGA>, 900 <&cru HCLK_RGA>; 901 pm_qos = <&qos_lcdc0>, 902 <&qos_lcdc1>, 903 <&qos_cif0>, 904 <&qos_cif1>, 905 <&qos_ipp>, 906 <&qos_rga>; 907 }; 908 909 power-domain@RK3066_PD_VIDEO { 910 reg = <RK3066_PD_VIDEO>; 911 clocks = <&cru ACLK_VDPU>, 912 <&cru ACLK_VEPU>, 913 <&cru HCLK_VDPU>, 914 <&cru HCLK_VEPU>; 915 pm_qos = <&qos_vpu>; 916 }; 917 918 power-domain@RK3066_PD_GPU { 919 reg = <RK3066_PD_GPU>; 920 clocks = <&cru ACLK_GPU>; 921 pm_qos = <&qos_gpu>; 922 }; 923 }; 924}; 925 926&pwm0 { 927 pinctrl-names = "active"; 928 pinctrl-0 = <&pwm0_out>; 929}; 930 931&pwm1 { 932 pinctrl-names = "active"; 933 pinctrl-0 = <&pwm1_out>; 934}; 935 936&pwm2 { 937 pinctrl-names = "active"; 938 pinctrl-0 = <&pwm2_out>; 939}; 940 941&pwm3 { 942 pinctrl-names = "active"; 943 pinctrl-0 = <&pwm3_out>; 944}; 945 946&spi0 { 947 pinctrl-names = "default"; 948 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 949}; 950 951&spi1 { 952 pinctrl-names = "default"; 953 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 954}; 955 956&uart0 { 957 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 958 dmas = <&dmac1_s 0>, <&dmac1_s 1>; 959 dma-names = "tx", "rx"; 960 pinctrl-names = "default"; 961 pinctrl-0 = <&uart0_xfer>; 962}; 963 964&uart1 { 965 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 966 dmas = <&dmac1_s 2>, <&dmac1_s 3>; 967 dma-names = "tx", "rx"; 968 pinctrl-names = "default"; 969 pinctrl-0 = <&uart1_xfer>; 970}; 971 972&uart2 { 973 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 974 dmas = <&dmac2 6>, <&dmac2 7>; 975 dma-names = "tx", "rx"; 976 pinctrl-names = "default"; 977 pinctrl-0 = <&uart2_xfer>; 978}; 979 980&uart3 { 981 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 982 dmas = <&dmac2 8>, <&dmac2 9>; 983 dma-names = "tx", "rx"; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&uart3_xfer>; 986}; 987 988&wdt { 989 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; 990}; 991 992&emac { 993 compatible = "rockchip,rk3066-emac"; 994}; 995