xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/rk3188.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * SPDX-License-Identifier:     GPL-2.0+ or X11
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/pinctrl/rockchip.h>
10#include <dt-bindings/clock/rk3188-cru.h>
11#include "rk3xxx.dtsi"
12
13/ {
14	compatible = "rockchip,rk3188";
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19		enable-method = "rockchip,rk3066-smp";
20
21		cpu0: cpu@0 {
22			device_type = "cpu";
23			compatible = "arm,cortex-a9";
24			next-level-cache = <&L2>;
25			reg = <0x0>;
26			operating-points = <
27				/* kHz    uV */
28				1608000 1350000
29				1416000 1250000
30				1200000 1150000
31				1008000 1075000
32				 816000  975000
33				 600000  950000
34				 504000  925000
35				 312000  875000
36			>;
37			clock-latency = <40000>;
38			clocks = <&cru ARMCLK>;
39		};
40		cpu@1 {
41			device_type = "cpu";
42			compatible = "arm,cortex-a9";
43			next-level-cache = <&L2>;
44			reg = <0x1>;
45		};
46		cpu@2 {
47			device_type = "cpu";
48			compatible = "arm,cortex-a9";
49			next-level-cache = <&L2>;
50			reg = <0x2>;
51		};
52		cpu@3 {
53			device_type = "cpu";
54			compatible = "arm,cortex-a9";
55			next-level-cache = <&L2>;
56			reg = <0x3>;
57		};
58	};
59
60	sram: sram@10080000 {
61		compatible = "mmio-sram";
62		reg = <0x10080000 0x8000>;
63		#address-cells = <1>;
64		#size-cells = <1>;
65		ranges = <0 0x10080000 0x8000>;
66
67		smp-sram@0 {
68			compatible = "rockchip,rk3066-smp-sram";
69			reg = <0x0 0x50>;
70		};
71	};
72
73	i2s0: i2s@1011a000 {
74		compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
75		reg = <0x1011a000 0x2000>;
76		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
77		#address-cells = <1>;
78		#size-cells = <0>;
79		pinctrl-names = "default";
80		pinctrl-0 = <&i2s0_bus>;
81		dmas = <&dmac1_s 6>, <&dmac1_s 7>;
82		dma-names = "tx", "rx";
83		clock-names = "i2s_hclk", "i2s_clk";
84		clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
85		rockchip,playback-channels = <2>;
86		rockchip,capture-channels = <2>;
87		status = "disabled";
88	};
89
90	spdif: sound@1011e000 {
91		compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
92		reg = <0x1011e000 0x2000>;
93		#sound-dai-cells = <0>;
94		clock-names = "hclk", "mclk";
95		clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
96		dmas = <&dmac1_s 8>;
97		dma-names = "tx";
98		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
99		pinctrl-names = "default";
100		pinctrl-0 = <&spdif_tx>;
101		status = "disabled";
102	};
103
104	cru: clock-controller@20000000 {
105		compatible = "rockchip,rk3188-cru";
106		reg = <0x20000000 0x1000>;
107		rockchip,grf = <&grf>;
108
109		#clock-cells = <1>;
110		#reset-cells = <1>;
111	};
112
113	efuse: efuse@20010000 {
114		compatible = "rockchip,rockchip-efuse";
115		reg = <0x20010000 0x4000>;
116		#address-cells = <1>;
117		#size-cells = <1>;
118		clocks = <&cru PCLK_EFUSE>;
119		clock-names = "pclk_efuse";
120
121		cpu_leakage: cpu_leakage@17 {
122			reg = <0x17 0x1>;
123		};
124	};
125
126	saradc: saradc@2006c000 {
127		compatible = "rockchip,saradc";
128		reg = <0x2006c000 0x100>;
129		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
130		#io-channel-cells = <1>;
131		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
132		clock-names = "saradc", "pclk_saradc";
133		status = "disabled";
134	};
135
136	timer3: timer@2000e000 {
137		compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
138		reg = <0x2000e000 0x20>;
139		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
140	};
141
142	usbphy: phy {
143		compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
144		rockchip,grf = <&grf>;
145		#address-cells = <1>;
146		#size-cells = <0>;
147		status = "disabled";
148
149		usbphy0: usb-phy@10c {
150			#phy-cells = <0>;
151			reg = <0x10c>;
152			clocks = <&cru SCLK_OTGPHY0>;
153			clock-names = "phyclk";
154			#clock-cells = <0>;
155		};
156
157		usbphy1: usb-phy@11c {
158			#phy-cells = <0>;
159			reg = <0x11c>;
160			clocks = <&cru SCLK_OTGPHY1>;
161			clock-names = "phyclk";
162			#clock-cells = <0>;
163		};
164	};
165
166	pinctrl: pinctrl {
167		compatible = "rockchip,rk3188-pinctrl";
168		rockchip,grf = <&grf>;
169		rockchip,pmu = <&pmu>;
170
171		#address-cells = <1>;
172		#size-cells = <1>;
173		ranges;
174
175		gpio0: gpio0@2000a000 {
176			compatible = "rockchip,gpio-bank";
177			reg = <0x2000a000 0x100>;
178			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
179			clocks = <&cru PCLK_GPIO0>;
180
181			gpio-controller;
182			#gpio-cells = <2>;
183
184			interrupt-controller;
185			#interrupt-cells = <2>;
186		};
187
188		gpio1: gpio1@2003c000 {
189			compatible = "rockchip,gpio-bank";
190			reg = <0x2003c000 0x100>;
191			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
192			clocks = <&cru PCLK_GPIO1>;
193
194			gpio-controller;
195			#gpio-cells = <2>;
196
197			interrupt-controller;
198			#interrupt-cells = <2>;
199		};
200
201		gpio2: gpio2@2003e000 {
202			compatible = "rockchip,gpio-bank";
203			reg = <0x2003e000 0x100>;
204			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
205			clocks = <&cru PCLK_GPIO2>;
206
207			gpio-controller;
208			#gpio-cells = <2>;
209
210			interrupt-controller;
211			#interrupt-cells = <2>;
212		};
213
214		gpio3: gpio3@20080000 {
215			compatible = "rockchip,gpio-bank";
216			reg = <0x20080000 0x100>;
217			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
218			clocks = <&cru PCLK_GPIO3>;
219
220			gpio-controller;
221			#gpio-cells = <2>;
222
223			interrupt-controller;
224			#interrupt-cells = <2>;
225		};
226
227		pcfg_pull_up: pcfg_pull_up {
228			bias-pull-up;
229		};
230
231		pcfg_pull_down: pcfg_pull_down {
232			bias-pull-down;
233		};
234
235		pcfg_pull_none: pcfg_pull_none {
236			bias-disable;
237		};
238
239		emmc {
240			emmc_clk: emmc-clk {
241				rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
242			};
243
244			emmc_cmd: emmc-cmd {
245				rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
246			};
247
248			emmc_rst: emmc-rst {
249				rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
250			};
251
252			/*
253			 * The data pins are shared between nandc and emmc and
254			 * not accessible through pinctrl. Also they should've
255			 * been already set correctly by firmware, as
256			 * flash/emmc is the boot-device.
257			 */
258		};
259
260		emac {
261			emac_xfer: emac-xfer {
262				rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
263						<RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
264						<RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
265						<RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
266						<RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
267						<RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
268						<RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
269						<RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
270			};
271
272			emac_mdio: emac-mdio {
273				rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
274						<RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
275			};
276		};
277
278		i2c0 {
279			i2c0_xfer: i2c0-xfer {
280				rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
281						<RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
282			};
283		};
284
285		i2c1 {
286			i2c1_xfer: i2c1-xfer {
287				rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
288						<RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
289			};
290		};
291
292		i2c2 {
293			i2c2_xfer: i2c2-xfer {
294				rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
295						<RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
296			};
297		};
298
299		i2c3 {
300			i2c3_xfer: i2c3-xfer {
301				rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
302						<RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
303			};
304		};
305
306		i2c4 {
307			i2c4_xfer: i2c4-xfer {
308				rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
309						<RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
310			};
311		};
312
313		pwm0 {
314			pwm0_out: pwm0-out {
315				rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
316			};
317		};
318
319		pwm1 {
320			pwm1_out: pwm1-out {
321				rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
322			};
323		};
324
325		pwm2 {
326			pwm2_out: pwm2-out {
327				rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
328			};
329		};
330
331		pwm3 {
332			pwm3_out: pwm3-out {
333				rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
334			};
335		};
336
337		spi0 {
338			spi0_clk: spi0-clk {
339				rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
340			};
341			spi0_cs0: spi0-cs0 {
342				rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
343			};
344			spi0_tx: spi0-tx {
345				rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
346			};
347			spi0_rx: spi0-rx {
348				rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
349			};
350			spi0_cs1: spi0-cs1 {
351				rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
352			};
353		};
354
355		spi1 {
356			spi1_clk: spi1-clk {
357				rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
358			};
359			spi1_cs0: spi1-cs0 {
360				rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
361			};
362			spi1_rx: spi1-rx {
363				rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
364			};
365			spi1_tx: spi1-tx {
366				rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
367			};
368			spi1_cs1: spi1-cs1 {
369				rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
370			};
371		};
372
373		uart0 {
374			uart0_xfer: uart0-xfer {
375				rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
376						<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
377			};
378
379			uart0_cts: uart0-cts {
380				rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
381			};
382
383			uart0_rts: uart0-rts {
384				rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
385			};
386		};
387
388		uart1 {
389			uart1_xfer: uart1-xfer {
390				rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
391						<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
392			};
393
394			uart1_cts: uart1-cts {
395				rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
396			};
397
398			uart1_rts: uart1-rts {
399				rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
400			};
401		};
402
403		uart2 {
404			uart2_xfer: uart2-xfer {
405				rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
406						<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
407			};
408			/* no rts / cts for uart2 */
409		};
410
411		uart3 {
412			uart3_xfer: uart3-xfer {
413				rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
414						<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
415			};
416
417			uart3_cts: uart3-cts {
418				rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
419			};
420
421			uart3_rts: uart3-rts {
422				rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
423			};
424		};
425
426		sd0 {
427			sd0_clk: sd0-clk {
428				rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
429			};
430
431			sd0_cmd: sd0-cmd {
432				rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
433			};
434
435			sd0_cd: sd0-cd {
436				rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
437			};
438
439			sd0_wp: sd0-wp {
440				rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
441			};
442
443			sd0_pwr: sd0-pwr {
444				rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
445			};
446
447			sd0_bus1: sd0-bus-width1 {
448				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
449			};
450
451			sd0_bus4: sd0-bus-width4 {
452				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
453						<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
454						<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
455						<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
456			};
457		};
458
459		sd1 {
460			sd1_clk: sd1-clk {
461				rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
462			};
463
464			sd1_cmd: sd1-cmd {
465				rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
466			};
467
468			sd1_cd: sd1-cd {
469				rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
470			};
471
472			sd1_wp: sd1-wp {
473				rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
474			};
475
476			sd1_bus1: sd1-bus-width1 {
477				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
478			};
479
480			sd1_bus4: sd1-bus-width4 {
481				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
482						<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
483						<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
484						<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
485			};
486		};
487
488		i2s0 {
489			i2s0_bus: i2s0-bus {
490				rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
491						<RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
492						<RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
493						<RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
494						<RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
495						<RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
496			};
497		};
498
499		spdif {
500			spdif_tx: spdif-tx {
501				rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
502			};
503		};
504	};
505};
506
507&emac {
508	compatible = "rockchip,rk3188-emac";
509};
510
511&global_timer {
512	interrupts = <GIC_PPI 11 0xf04>;
513};
514
515&grf {
516	compatible = "rockchip,rk3188-grf", "syscon";
517};
518
519&local_timer {
520	interrupts = <GIC_PPI 13 0xf04>;
521};
522
523&i2c0 {
524	compatible = "rockchip,rk3188-i2c";
525	pinctrl-names = "default";
526	pinctrl-0 = <&i2c0_xfer>;
527};
528
529&i2c1 {
530	compatible = "rockchip,rk3188-i2c";
531	pinctrl-names = "default";
532	pinctrl-0 = <&i2c1_xfer>;
533};
534
535&i2c2 {
536	compatible = "rockchip,rk3188-i2c";
537	pinctrl-names = "default";
538	pinctrl-0 = <&i2c2_xfer>;
539};
540
541&i2c3 {
542	compatible = "rockchip,rk3188-i2c";
543	pinctrl-names = "default";
544	pinctrl-0 = <&i2c3_xfer>;
545};
546
547&i2c4 {
548	compatible = "rockchip,rk3188-i2c";
549	pinctrl-names = "default";
550	pinctrl-0 = <&i2c4_xfer>;
551};
552
553&pmu {
554	compatible = "rockchip,rk3188-pmu", "syscon";
555};
556
557&pwm0 {
558	pinctrl-names = "active";
559	pinctrl-0 = <&pwm0_out>;
560};
561
562&pwm1 {
563	pinctrl-names = "active";
564	pinctrl-0 = <&pwm1_out>;
565};
566
567&pwm2 {
568	pinctrl-names = "active";
569	pinctrl-0 = <&pwm2_out>;
570};
571
572&pwm3 {
573	pinctrl-names = "active";
574	pinctrl-0 = <&pwm3_out>;
575};
576
577&spi0 {
578	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
579	pinctrl-names = "default";
580	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
581};
582
583&spi1 {
584	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
585	pinctrl-names = "default";
586	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
587};
588
589&uart0 {
590	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
591	pinctrl-names = "default";
592	pinctrl-0 = <&uart0_xfer>;
593};
594
595&uart1 {
596	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
597	pinctrl-names = "default";
598	pinctrl-0 = <&uart1_xfer>;
599};
600
601&uart2 {
602	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
603	pinctrl-names = "default";
604	pinctrl-0 = <&uart2_xfer>;
605};
606
607&uart3 {
608	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
609	pinctrl-names = "default";
610	pinctrl-0 = <&uart3_xfer>;
611};
612
613&wdt {
614	compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
615};
616