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Searched refs:postdiv2 (Results 1 – 24 of 24) sorted by relevance

/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_pll.c84 u32 *postdiv2, in rockchip_pll_clk_set_postdiv() argument
91 for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) { in rockchip_pll_clk_set_postdiv()
92 freq = fout_hz * (*postdiv1) * (*postdiv2); in rockchip_pll_clk_set_postdiv()
104 *postdiv2 = 1; in rockchip_pll_clk_set_postdiv()
117 u32 f_frac, postdiv1, postdiv2; in rockchip_pll_clk_set_by_auto() local
123 rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco); in rockchip_pll_clk_set_by_auto()
125 rate_table->postdiv2 = postdiv2; in rockchip_pll_clk_set_by_auto()
142 rate_table->postdiv2); in rockchip_pll_clk_set_by_auto()
147 rate_table->postdiv1, rate_table->postdiv2, foutvco); in rockchip_pll_clk_set_by_auto()
307 __func__, rate->rate, rate->postdiv2, rate->dsmpd, rate->frac); in rk3036_pll_set_rate()
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H A Dclk_rk3399.c39 u32 postdiv2; member
51 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz};
344 u32 refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
357 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rkclk_pll_get_rate()
359 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
370 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
375 div->postdiv2, vco_khz, output_khz); in rkclk_set_pll()
396 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | in rkclk_set_pll()
448 u32 postdiv1, postdiv2 = 1; in pll_para_config() local
463 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); in pll_para_config()
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H A Dclk_rk3036.c52 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
70 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
75 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
89 (div->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()
204 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
233 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rkclk_pll_get_rate()
235 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
H A Dclk_rv1108.c34 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
73 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
77 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
96 div->postdiv2 << POSTDIV2_SHIFT | in rkclk_set_pll()
120 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
133 postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT; in rkclk_pll_get_rate()
135 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
H A Dclk_px30.c39 .postdiv2 = _postdiv2, \
111 u32 postdiv1, postdiv2 = 1; in pll_clk_set_by_auto() local
126 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); in pll_clk_set_by_auto()
127 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); in pll_clk_set_by_auto()
130 vco_khz = rate_khz * postdiv1 * postdiv2; in pll_clk_set_by_auto()
133 postdiv2 > max_postdiv2) { in pll_clk_set_by_auto()
140 rate->postdiv2 = postdiv2; in pll_clk_set_by_auto()
229 output_hz = vco_hz / rate->postdiv1 / rate->postdiv2; in rkclk_set_pll()
233 rate->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
253 (rate->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()
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/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_cru.c62 u32 postdiv1, fbdiv, dsmpd, postdiv2, refdiv, frac, bypass; in rk628_cru_clk_get_rate_pll() local
102 postdiv2 = (con1 & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rk628_cru_clk_get_rate_pll()
121 do_div(foutpostdiv, postdiv2); in rk628_cru_clk_get_rate_pll()
132 u8 dsmpd = 1, postdiv1 = 0, postdiv2 = 0, refdiv = 0; in rk628_cru_clk_set_rate_pll() local
181 for (postdiv2 = 1; postdiv2 < 8; postdiv2++) { in rk628_cru_clk_set_rate_pll()
182 if (postdiv % postdiv2) in rk628_cru_clk_set_rate_pll()
184 postdiv1 = postdiv / postdiv2; in rk628_cru_clk_set_rate_pll()
188 if (postdiv2 > 7) in rk628_cru_clk_set_rate_pll()
195 fout *= postdiv1 * postdiv2; in rk628_cru_clk_set_rate_pll()
198 postdiv2 = 1; in rk628_cru_clk_set_rate_pll()
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/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_rk3328.c79 unsigned int refdiv, postdiv1, postdiv2, fbdiv; in rkclk_set_dpll() local
86 postdiv2 = 2; in rkclk_set_dpll()
89 postdiv2 = 1; in rkclk_set_dpll()
92 postdiv2 = 1; in rkclk_set_dpll()
95 postdiv2 = 1; in rkclk_set_dpll()
98 postdiv2 = 1; in rkclk_set_dpll()
101 postdiv2 = 1; in rkclk_set_dpll()
103 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
107 writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv), in rkclk_set_dpll()
H A Dsdram_px30.c78 unsigned int refdiv, postdiv1, postdiv2, fbdiv; in rkclk_set_dpll() local
85 postdiv2 = 2; in rkclk_set_dpll()
88 postdiv2 = 1; in rkclk_set_dpll()
91 postdiv2 = 1; in rkclk_set_dpll()
94 postdiv2 = 1; in rkclk_set_dpll()
97 postdiv2 = 1; in rkclk_set_dpll()
100 postdiv2 = 1; in rkclk_set_dpll()
102 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
107 writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv), in rkclk_set_dpll()
H A Dsdram_rk3308.c93 pll_priv->postdiv2 << POSTDIV2_SHIFT | in pll_set()
135 rk3308_pll_div.postdiv2 = 1; in rkdclk_init()
145 rk3308_pll_div.postdiv2 = 1; in rkdclk_init()
153 rk3308_pll_div.postdiv2 = 1; in rkdclk_init()
189 rk3308_pll_div.postdiv2 = 1; in rkdclk_init()
197 rk3308_pll_div.postdiv2 = 1; in rkdclk_init()
266 rk3308_pll_div.postdiv2 = 1; in rkdclk_init()
329 rk3308_pll_div.postdiv2 = 1; in rkdclk_init()
H A Dsdram_rv1108.c51 params_priv->dpll_init_cfg.postdiv2 << POSTDIV2_SHIFT | in rkdclk_init()
H A Dsdram_rv1126.c323 unsigned int refdiv, postdiv1, postdiv2, fbdiv; in rkclk_set_dpll() local
338 postdiv2 = 4; in rkclk_set_dpll()
341 postdiv2 = 4; in rkclk_set_dpll()
344 postdiv2 = 2; in rkclk_set_dpll()
347 postdiv2 = 2; in rkclk_set_dpll()
350 postdiv2 = 1; in rkclk_set_dpll()
353 postdiv2 = 1; in rkclk_set_dpll()
355 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
374 writel(DSMPD(dsmpd) | POSTDIV2(postdiv2) | REFDIV(refdiv), in rkclk_set_dpll()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dclock.h75 .postdiv2 = _postdiv2, \
99 unsigned int postdiv2; member
H A Dcru_rk3036.h70 u32 postdiv2; member
H A Dcru_rv1108.h58 u32 postdiv2; member
H A Dcru_rv1103b.h120 unsigned int postdiv2; member
H A Dcru_rv1106.h124 unsigned int postdiv2; member
H A Dcru_rk3506.h89 unsigned int postdiv2; member
H A Dcru_rv1126.h144 unsigned int postdiv2; member
H A Dcru_px30.h120 unsigned int postdiv2; member
H A Dcru_rk3528.h110 unsigned int postdiv2; member
H A Dcru_rk3562.h145 unsigned int postdiv2; member
H A Dcru_rv1126b.h149 unsigned int postdiv2; member
H A Dcru_rk3568.h117 unsigned int postdiv2; member
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c343 (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT | in rkdclk_init()