13f2ef139Shuang lin /* 23f2ef139Shuang lin * (C) Copyright 2015 Rockchip Electronics Co., Ltd 33f2ef139Shuang lin * 43f2ef139Shuang lin * SPDX-License-Identifier: GPL-2.0+ 53f2ef139Shuang lin */ 63f2ef139Shuang lin #ifndef _ASM_ARCH_CRU_RK3036_H 73f2ef139Shuang lin #define _ASM_ARCH_CRU_RK3036_H 83f2ef139Shuang lin 93f2ef139Shuang lin #include <common.h> 103f2ef139Shuang lin 113f2ef139Shuang lin #define OSC_HZ (24 * 1000 * 1000) 123f2ef139Shuang lin 133f2ef139Shuang lin #define APLL_HZ (600 * 1000000) 143f2ef139Shuang lin #define GPLL_HZ (594 * 1000000) 153f2ef139Shuang lin 163f2ef139Shuang lin #define CORE_PERI_HZ 150000000 173f2ef139Shuang lin #define CORE_ACLK_HZ 300000000 183f2ef139Shuang lin 191960b010SKever Yang #define BUS_ACLK_HZ 148500000 201960b010SKever Yang #define BUS_HCLK_HZ 148500000 211960b010SKever Yang #define BUS_PCLK_HZ 74250000 223f2ef139Shuang lin 233f2ef139Shuang lin #define PERI_ACLK_HZ 148500000 243f2ef139Shuang lin #define PERI_HCLK_HZ 148500000 253f2ef139Shuang lin #define PERI_PCLK_HZ 74250000 263f2ef139Shuang lin 2792ac73e4SSimon Glass /* Private data for the clock driver - used by rockchip_get_cru() */ 2892ac73e4SSimon Glass struct rk3036_clk_priv { 2992ac73e4SSimon Glass struct rk3036_cru *cru; 3092ac73e4SSimon Glass ulong rate; 313a1c76d9SElaine Zhang ulong armclk_hz; 323a1c76d9SElaine Zhang ulong armclk_enter_hz; 333a1c76d9SElaine Zhang ulong armclk_init_hz; 343a1c76d9SElaine Zhang bool sync_kernel; 353a1c76d9SElaine Zhang bool set_armclk_rate; 3692ac73e4SSimon Glass }; 3792ac73e4SSimon Glass 383f2ef139Shuang lin struct rk3036_cru { 393f2ef139Shuang lin struct rk3036_pll { 403f2ef139Shuang lin unsigned int con0; 413f2ef139Shuang lin unsigned int con1; 423f2ef139Shuang lin unsigned int con2; 433f2ef139Shuang lin unsigned int con3; 443f2ef139Shuang lin } pll[4]; 453f2ef139Shuang lin unsigned int cru_mode_con; 463f2ef139Shuang lin unsigned int cru_clksel_con[35]; 473f2ef139Shuang lin unsigned int cru_clkgate_con[11]; 483f2ef139Shuang lin unsigned int reserved; 493f2ef139Shuang lin unsigned int cru_glb_srst_fst_value; 503f2ef139Shuang lin unsigned int cru_glb_srst_snd_value; 513f2ef139Shuang lin unsigned int reserved1[2]; 523f2ef139Shuang lin unsigned int cru_softrst_con[9]; 533f2ef139Shuang lin unsigned int cru_misc_con; 543f2ef139Shuang lin unsigned int reserved2[2]; 553f2ef139Shuang lin unsigned int cru_glb_cnt_th; 563f2ef139Shuang lin unsigned int cru_sdmmc_con[2]; 573f2ef139Shuang lin unsigned int cru_sdio_con[2]; 583f2ef139Shuang lin unsigned int cru_emmc_con[2]; 593f2ef139Shuang lin unsigned int reserved3; 603f2ef139Shuang lin unsigned int cru_rst_st; 613f2ef139Shuang lin unsigned int reserved4[0x23]; 623f2ef139Shuang lin unsigned int cru_pll_mask_con; 633f2ef139Shuang lin }; 643f2ef139Shuang lin check_member(rk3036_cru, cru_pll_mask_con, 0x01f0); 653f2ef139Shuang lin 663f2ef139Shuang lin struct pll_div { 673f2ef139Shuang lin u32 refdiv; 683f2ef139Shuang lin u32 fbdiv; 693f2ef139Shuang lin u32 postdiv1; 703f2ef139Shuang lin u32 postdiv2; 713f2ef139Shuang lin u32 frac; 723f2ef139Shuang lin }; 733f2ef139Shuang lin 743a1c76d9SElaine Zhang struct rk3036_clk_info { 753a1c76d9SElaine Zhang unsigned long id; 763a1c76d9SElaine Zhang char *name; 773a1c76d9SElaine Zhang bool is_cru; 783a1c76d9SElaine Zhang }; 793a1c76d9SElaine Zhang 803f2ef139Shuang lin enum { 813f2ef139Shuang lin /* PLLCON0*/ 823f2ef139Shuang lin PLL_POSTDIV1_SHIFT = 12, 8337943aaeSKever Yang PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 843f2ef139Shuang lin PLL_FBDIV_SHIFT = 0, 8537943aaeSKever Yang PLL_FBDIV_MASK = 0xfff, 863f2ef139Shuang lin 873f2ef139Shuang lin /* PLLCON1 */ 883f2ef139Shuang lin PLL_RST_SHIFT = 14, 8900fbb281SDavid Wu PLL_PD_SHIFT = 13, 9000fbb281SDavid Wu PLL_PD_MASK = 1 << PLL_PD_SHIFT, 9137943aaeSKever Yang PLL_DSMPD_SHIFT = 12, 9237943aaeSKever Yang PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 9337943aaeSKever Yang PLL_LOCK_STATUS_SHIFT = 10, 9437943aaeSKever Yang PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 9537943aaeSKever Yang PLL_POSTDIV2_SHIFT = 6, 9637943aaeSKever Yang PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 9737943aaeSKever Yang PLL_REFDIV_SHIFT = 0, 9837943aaeSKever Yang PLL_REFDIV_MASK = 0x3f, 993f2ef139Shuang lin 1003f2ef139Shuang lin /* CRU_MODE */ 1013f2ef139Shuang lin GPLL_MODE_SHIFT = 12, 10237943aaeSKever Yang GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, 1033f2ef139Shuang lin GPLL_MODE_SLOW = 0, 1043f2ef139Shuang lin GPLL_MODE_NORM, 1053f2ef139Shuang lin GPLL_MODE_DEEP, 1063f2ef139Shuang lin DPLL_MODE_SHIFT = 4, 10737943aaeSKever Yang DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, 1083f2ef139Shuang lin DPLL_MODE_SLOW = 0, 1093f2ef139Shuang lin DPLL_MODE_NORM, 1103f2ef139Shuang lin APLL_MODE_SHIFT = 0, 11137943aaeSKever Yang APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, 1123f2ef139Shuang lin APLL_MODE_SLOW = 0, 1133f2ef139Shuang lin APLL_MODE_NORM, 1143f2ef139Shuang lin 1153f2ef139Shuang lin /* CRU_CLK_SEL0_CON */ 11637943aaeSKever Yang BUS_ACLK_PLL_SEL_SHIFT = 14, 11737943aaeSKever Yang BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, 11837943aaeSKever Yang BUS_ACLK_PLL_SEL_APLL = 0, 11937943aaeSKever Yang BUS_ACLK_PLL_SEL_DPLL, 12037943aaeSKever Yang BUS_ACLK_PLL_SEL_GPLL, 12137943aaeSKever Yang BUS_ACLK_DIV_SHIFT = 8, 12237943aaeSKever Yang BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 1233f2ef139Shuang lin CORE_CLK_PLL_SEL_SHIFT = 7, 12437943aaeSKever Yang CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 1253f2ef139Shuang lin CORE_CLK_PLL_SEL_APLL = 0, 1263f2ef139Shuang lin CORE_CLK_PLL_SEL_GPLL, 1273f2ef139Shuang lin CORE_DIV_CON_SHIFT = 0, 12837943aaeSKever Yang CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 1293f2ef139Shuang lin 1303f2ef139Shuang lin /* CRU_CLK_SEL1_CON */ 13137943aaeSKever Yang BUS_PCLK_DIV_SHIFT = 12, 13237943aaeSKever Yang BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, 13337943aaeSKever Yang BUS_HCLK_DIV_SHIFT = 8, 13437943aaeSKever Yang BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, 1353f2ef139Shuang lin CORE_ACLK_DIV_SHIFT = 4, 13637943aaeSKever Yang CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, 1373f2ef139Shuang lin CORE_PERI_DIV_SHIFT = 0, 13837943aaeSKever Yang CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, 1393f2ef139Shuang lin 1403f2ef139Shuang lin /* CRU_CLKSEL10_CON */ 1413f2ef139Shuang lin PERI_PLL_SEL_SHIFT = 14, 14237943aaeSKever Yang PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, 1433f2ef139Shuang lin PERI_PLL_APLL = 0, 1443f2ef139Shuang lin PERI_PLL_DPLL, 1453f2ef139Shuang lin PERI_PLL_GPLL, 1463f2ef139Shuang lin PERI_PCLK_DIV_SHIFT = 12, 14737943aaeSKever Yang PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, 1483f2ef139Shuang lin PERI_HCLK_DIV_SHIFT = 8, 14937943aaeSKever Yang PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, 1503f2ef139Shuang lin PERI_ACLK_DIV_SHIFT = 0, 15137943aaeSKever Yang PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 1523f2ef139Shuang lin 1533f2ef139Shuang lin /* CRU_CLKSEL11_CON */ 1543f2ef139Shuang lin SDIO_DIV_SHIFT = 8, 15537943aaeSKever Yang SDIO_DIV_MASK = 0x7f << SDIO_DIV_SHIFT, 1563f2ef139Shuang lin MMC0_DIV_SHIFT = 0, 15737943aaeSKever Yang MMC0_DIV_MASK = 0x7f << MMC0_DIV_SHIFT, 1583f2ef139Shuang lin 1593f2ef139Shuang lin /* CRU_CLKSEL12_CON */ 1603f2ef139Shuang lin EMMC_PLL_SHIFT = 12, 16137943aaeSKever Yang EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 1623f2ef139Shuang lin EMMC_SEL_APLL = 0, 1633f2ef139Shuang lin EMMC_SEL_DPLL, 1643f2ef139Shuang lin EMMC_SEL_GPLL, 1653f2ef139Shuang lin EMMC_SEL_24M, 1663f2ef139Shuang lin SDIO_PLL_SHIFT = 10, 16737943aaeSKever Yang SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, 1683f2ef139Shuang lin SDIO_SEL_APLL = 0, 1693f2ef139Shuang lin SDIO_SEL_DPLL, 1703f2ef139Shuang lin SDIO_SEL_GPLL, 1713f2ef139Shuang lin SDIO_SEL_24M, 1723f2ef139Shuang lin MMC0_PLL_SHIFT = 8, 17337943aaeSKever Yang MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, 1743f2ef139Shuang lin MMC0_SEL_APLL = 0, 1753f2ef139Shuang lin MMC0_SEL_DPLL, 1763f2ef139Shuang lin MMC0_SEL_GPLL, 1773f2ef139Shuang lin MMC0_SEL_24M, 1783f2ef139Shuang lin EMMC_DIV_SHIFT = 0, 17937943aaeSKever Yang EMMC_DIV_MASK = 0x7f << EMMC_DIV_SHIFT, 1803f2ef139Shuang lin 181904b267dSElaine Zhang /* CRU_CLKSEL16_CON */ 182904b267dSElaine Zhang NANDC_DIV_SHIFT = 10, 183904b267dSElaine Zhang NANDC_DIV_MASK = 0x1f << NANDC_DIV_SHIFT, 184904b267dSElaine Zhang NANDC_PLL_SHIFT = 8, 185904b267dSElaine Zhang NANDC_PLL_MASK = 3 << NANDC_PLL_SHIFT, 186904b267dSElaine Zhang NANDC_SEL_APLL = 0, 187904b267dSElaine Zhang NANDC_SEL_DPLL, 188904b267dSElaine Zhang NANDC_SEL_GPLL, 189904b267dSElaine Zhang 190*df77e7a3SElaine Zhang /* CLKSEL_CON25 */ 191*df77e7a3SElaine Zhang SPI_PLL_SEL_SHIFT = 8, 192*df77e7a3SElaine Zhang SPI_PLL_SEL_MASK = 0x3 << SPI_PLL_SEL_SHIFT, 193*df77e7a3SElaine Zhang SPI_PLL_SEL_APLL = 0, 194*df77e7a3SElaine Zhang SPI_PLL_SEL_DPLL, 195*df77e7a3SElaine Zhang SPI_PLL_SEL_GPLL, 196*df77e7a3SElaine Zhang SPI_DIV_SHIFT = 0, 197*df77e7a3SElaine Zhang SPI_DIV_MASK = 0x7f << SPI_DIV_SHIFT, 198*df77e7a3SElaine Zhang 19915ede2a1SFinley Xiao /* CRU_CLKSEL28_CON */ 20015ede2a1SFinley Xiao LCDC_DCLK_DIV_SHIFT = 8, 20115ede2a1SFinley Xiao LCDC_DCLK_DIV_MASK = 0xff << LCDC_DCLK_DIV_SHIFT, 20215ede2a1SFinley Xiao LCDC_DCLK_SEL_SHIFT = 0, 20315ede2a1SFinley Xiao LCDC_DCLK_SEL_MASK = 0x3 << LCDC_DCLK_SEL_SHIFT, 20415ede2a1SFinley Xiao LCDC_DCLK_SEL_APLL = 0, 20515ede2a1SFinley Xiao LCDC_DCLK_SEL_DPLL, 20615ede2a1SFinley Xiao LCDC_DCLK_SEL_GPLL, 20715ede2a1SFinley Xiao 20815ede2a1SFinley Xiao /* CRU_CLKSEL31_CON */ 20915ede2a1SFinley Xiao LCDC_ACLK_SEL_SHIFT = 14, 21015ede2a1SFinley Xiao LCDC_ACLK_SEL_MASK = 0x3 << LCDC_ACLK_SEL_SHIFT, 21115ede2a1SFinley Xiao LCDC_ACLK_SEL_APLL = 0, 21215ede2a1SFinley Xiao LCDC_ACLK_SEL_DPLL, 21315ede2a1SFinley Xiao LCDC_ACLK_SEL_GPLL, 21415ede2a1SFinley Xiao LCDC_ACLK_DIV_SHIFT = 8, 21515ede2a1SFinley Xiao LCDC_ACLK_DIV_MASK = 0x1f << LCDC_ACLK_DIV_SHIFT, 21615ede2a1SFinley Xiao 2173f2ef139Shuang lin /* CRU_SOFTRST5_CON */ 2183f2ef139Shuang lin DDRCTRL_PSRST_SHIFT = 11, 2193f2ef139Shuang lin DDRCTRL_SRST_SHIFT = 10, 2203f2ef139Shuang lin DDRPHY_PSRST_SHIFT = 9, 2213f2ef139Shuang lin DDRPHY_SRST_SHIFT = 8, 2223f2ef139Shuang lin }; 2233f2ef139Shuang lin #endif 224