62 	u32 postdiv1, fbdiv, dsmpd, postdiv2, refdiv, frac, bypass;  in rk628_cru_clk_get_rate_pll()  local
102 	postdiv2 = (con1 & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;  in rk628_cru_clk_get_rate_pll()
121 	do_div(foutpostdiv, postdiv2);  in rk628_cru_clk_get_rate_pll()
132 	u8 dsmpd = 1, postdiv1 = 0, postdiv2 = 0, refdiv = 0;  in rk628_cru_clk_set_rate_pll()  local
181 			for (postdiv2 = 1; postdiv2 < 8; postdiv2++) {  in rk628_cru_clk_set_rate_pll()
182 				if (postdiv % postdiv2)  in rk628_cru_clk_set_rate_pll()
184 				postdiv1 = postdiv / postdiv2;  in rk628_cru_clk_set_rate_pll()
188 			if (postdiv2 > 7)  in rk628_cru_clk_set_rate_pll()
195 		fout *= postdiv1 * postdiv2;  in rk628_cru_clk_set_rate_pll()
198 		postdiv2 = 1;  in rk628_cru_clk_set_rate_pll()
252 	do_div(foutpostdiv, postdiv2);  in rk628_cru_clk_set_rate_pll()
258 			PLL_DSMPD(dsmpd) | PLL_POSTDIV2(postdiv2) |  in rk628_cru_clk_set_rate_pll()